Cadence Design Systems unveiled the industry’s first silicon-proven, long-reach 112G SerDes IP in 7nm. The Cadence 7nm 112G PAM-4 SerDes IP delivers industry-leading power, performance and area (PPA) efficiency required to build high-port density networking products for next-generation cloud-scale and telco datacenters. Cadence has been working closely with early adopter customers, who have expressed strong interest in this innovative technology. Cadence is now ready to engage broadly with customers to enable their next-generation high-performance computing (HPC) ASICs, machine learning accelerators, and switch fabric SoCs.
Escalating mobile data consumption, burgeoning AI and machine learning applications, and emerging 5G communications requirements demand ever-increasing bandwidth, straining the existing cloud datacenter server, storage and networking infrastructure. Early adopters in the high-end cloud datacenter market are now installing 400G Ethernet ports, with 400G Ethernet expected to go mainstream in 2020 as early adopters begin 800G Ethernet deployment. 112G SerDes technology doubles the data rate of 56G SerDes, meeting the exploding high-speed connectivity needs for emerging data-intensive applications such as machine learning and neural networks.