Cadence Design Systems has just made available a new suite of SoC automotive functional safety verification tools for reducing by 50 percent the effort required by automotive designers need to prepare their SoC designs for ISO 26262 compliance.
According to Charlie Huang, executive vice president, Worldwide Field Operations and System & Verification Group at Cadence, it is an expansion of the company's Incisive functional verification tools and includes new fault injection and safety verification techniques for helping automotive engineers automate ISO 26262 compliance for traceability, safety verification and tool confidence level (TCL).
He said the Incisive Functional Safety Simulator and Functional Safety Analysis technologies are part of the Cadence System Development Suite (SDS), addressing the largest and most complex verification and hardware-software co-development challenges faced by semiconductor and system companies.
The Incisive tools, he said, reduce the compliance effort by automating the time-intensive manual verification process of fault injection and result analysis for IP, System-on-Chip (SoC) and system designs. The new simulator operates within the Incisive Enterprise Simulator compiled-code engine, boosting runtime performance up to 10x and providing the seamless reuse of the functional and mixed-signal verification environments to accelerate the time to develop safety verification versus the interpreted Incisive Verifault-XL engine traditionally used in functional safety simulation.
Because the ability of safety systems to detect faults is the critical measurement for ISO 26262 compliance, Huang said the Functional Safety Analysis capability allows the safety engineer to automatically generate a safety verification regression from the fault dictionary created by the simulator and enables the tracking of millions of detected, partially detected, and undetected faults introduced into simulation to verify the safety systems in a design.
By automating the tracking of these safety metrics, he said, it cuts down on the man-years of effort, and provides the traceable audit trail needed in the systems design chain from semiconductor to OEM suppliers.