Cadence Virtuoso IC design platform gains significant improvements - Embedded.com

Cadence Virtuoso IC design platform gains significant improvements

Cadence Design Systems recently made some improvements to its Virtuoso IC design platform, extending the performance, capacity, and usability of Virtuoso IC6.1.4. These enhancements will benefit design teams working along the full spectrum of design complexity, from the most advanced-node, cutting-edge designs to more traditional chips. The new release has been extended to work efficiently at advanced nodes down to 28 nm and now supports 64-bit processing.

The Virtuoso Space-Based Router has been integrated into the Virtuoso Layout Suite cockpit, making it easier to access. Hence, it now provides design teams a single common router they can use from start to finish to help ensure consistent results. Additional time-saving, quality-enhancing updates have been made to the Virtuoso Analog Design Environment XL, and Cadence design constraints technology.

Improvements to the Virtuoso Analog Design Environment XL include new display capabilities within the product that can now produce more, and better, datasheets. The ability of Virtuoso Analog Design Environment XL to analyze multiple tests simultaneously, including those across corner and statistical variations, helps engineers pick the best circuit design directions early in the design cycle, and verify those choices efficiently post implementation.

The new release extends the Cadence ExpressPcells capability to support multiple-user sites. Now customers can use their vast libraries of SKILL-parameterized cells anywhere and see up to an 8X performance improvement. The analog display technology can now handle multi-gigabyte waveform files more efficiently. Also, the 2-Gbyte limit on waveform databases has been removed to account for today's larger, more complex designs. More information is available at www.cadence.com.

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