Cambridge Consultants to show new 16-bit processor core in Grenoble - Embedded.com

Cambridge Consultants to show new 16-bit processor core in Grenoble

LONDON — Cambridge Consultants Ltd. (Cambridge, England) is to show a new 16-bit RISC microprocessor royalty-free IP core at the Design & Reuse IP-SoC conference in Grenoble, France on 7 and 8 December.

The 16-bit XAP4 is on a 0.18 micron CMOS fabrication process and can deliver up to 63 Dhrystone MIPS at a clock frequency of 117 MHz. This benchmark performance of 0.54 MIPS/MHz is a 50% improvement over the company's previous 16-bit processor, XAP2, which has been manufactured in hundreds of millions by licensees such as CSR, and in ZigBee radios, automotive devices and low-power industrial and medical sensors.

The XAP4 has both 16-bit data and address buses and is capable of running programs up to 64 kbytes. The first implementation of the processor has a two-stage pipelined Von Neumann architecture. It is delivered to licensees as a soft IP core in Verilog RTL that can be synthesized in as few as 12k gates for ASICs where die size and power consumption must be as small as possible.

Cambridge Consultants has already delivered XAP4 to one licensee and is in discussion with other prospective customers at present.

Alistair Morfey, a technology director at Cambridge Consultants, said, “Some 32-bit cores offer similar code density when run in their 16-bit mode, but designers are still paying for a 32-bit wide core and RAM inside their ASIC, which will cost twice as much in silicon as a 16-bit system. In fact, there are probably hundreds of ASIC designs out there using more expensive 32-bit processor cores, when an advanced 16-bit core would do just as well.”

Cambridge Consultants' microprocessor core line-up also includes the 32-bit XAP3 while in development is the XAP5 that also uses 16-bit data but extends the address bus to 24-bits, providing support for larger program sizes up to 16 Mbytes. All these processor cores include SIF debug logic, which provides full control over the processor and access to its debug registers, together with non-invasive access to any part of the processor's memory map for data acquisition while a system is running.

All the processors include hardware support for privileged operating system modes where code running in user mode cannot corrupt supervisor or interrupt code. Code is position independent and there is also support for unaligned data access, making programs easy to port and quick to run. Most programs will be written in C and the processors feature direct support for many of the language constructs, which results in higher code density. There is hardware support for rapid context switching, for example, when interrupts occur, and there are multi-cycle instructions to speed up multiply, divide and block copy operations.

All the XAP microprocessors are supported by Cambridge Consukltants' xIDE integrated software development and debug environment, which includes a programmer's editor, assembler, debug interface, instruction set simulator, project build manager and GCC compiler, which provides the path for programming in C++. The XAP cores are delivered in Verilog RTL complete with software and debug tools.

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