Camera modules, image sensor wafer-level packaging, and silicon layout - Embedded.com

Camera modules, image sensor wafer-level packaging, and silicon layout

Considerable effort is usually expended on optimizing the layout of semiconductor devices to minimize their area. This strategy boosts the number of die per wafer and hence minimizes the unit die cost. CMOS image sensors are subject to different economics because a lens train and a protective cover for the imager die are integral to solid state camera modules and their assembly processes. These considerations dictate that the silicon layout must be compromised in order to achieve the lowest cost and smallest form factor camera modules.

Solid state optical sensors
Solid state optical sensors are finding application in an ever-widening variety of products. The largest markets by volume are camera modules for mobile phones, optical mice and digital cameras (see Figure 1 ). Solid state optical sensors are also utilized in large quantities in Web cams, document copiers, bar code readers, camcorders and positional control systems. These are large markets, which are growing rapidly, many exhibiting compound annual growth rates in double digits [Prismark, 2006]. More than two million cameras are made daily purely for inclusion in mobile phones.


Figure 1: The five largest markets for solid state image sensors in 2005.

The majority of solid state image sensors are based on complementary metal-oxide semiconductor (CMOS) technology as this provides a more integrated solution than competing approaches like CCD (Charged-Coupled Device). A CMOS image sensor comprises a 2D array of solar cells that provide the electro-optic conversion function, together with additional electronics for picture and power management. Each light-sensitive area on a chip with its associated electronics is referred to as a picture element, or “pixel” (see Figure 2 ).


Figure 2: One pixel of a solid state image sensor. The light-sensitive area is smaller than the pixel dimensions to allow for the integrated electronics.

On-chip real estate is required to house the electronics necessary to provide functionality to the pixel. Consequently, the dimensions of the solar cell in each pixel have to be decreased in proportion, which in turn adversely affects the ability of the image sensor to function in conditions where the light intensity is low. In order to compensate for the light loss, a micro lens is placed on each pixel. Micro lenses are pseudo-hemispherical in shape and serve to focus all of the light that impinges on each pixel onto the light-sensitive area, as illustrated in Figure 3 . In a modern solid state image sensor, the pixels will measure about 2µm on a side, so the micro lenses are of similar height.


Figure 3: Micro lenses are used to focus the incident light on each pixel on to the light-sensitive area, increasing the low light sensitivity of the image sensor.

However, these micro lenses add significant constraints in terms of processing and packaging the image sensors. First, to function accurately, an air space must exist directly above the lenses, as any material in direct contact with these micro lenses will alter their optical performance. Second, the micro lenses are very susceptible to particulate contamination. Micro lenses are generally composed of soft, polymeric materials, so foreign particles can easily damage them or become lodged on the surface of the lenses [Chowdhury, 2006]. Third, the micro lens manufacturing process often contains a melting step to produce the curved features, resulting in structures with limited temperature stability that restricts the range and duration of subsequent thermal excursions. Nevertheless, the optical benefits outweigh the other limitations, and all quality CMOS image sensors are provided with micro lenses as standard procedure.

Next: Solid state camera modules
Solid state camera modules
At a minimum, a solid state camera module consists of a lens assembly and an image sensor attached to a laminate substrate. A cross section through a typical solid state camera module is shown Figure 4 . The number of lens elements varies based on the requirements of the optical design, but in most camera phones, there are usually two to four lenses. One lens is usually made of glass, while the others are manufactured by injection molding of plastic. An infrared filter will also be included somewhere in the optical train, either as a separate element or as a coating on one of the lenses, because silicon photo detectors are sensitive to longer wavelengths than the human eye can perceive.


Figure 4: Schematic of typical camera module using chip-on-board technology to mount the image sensor on the PCB (or flexible substrate).

Chip-on-board (COB) assembly is the dominant process used today for camera module manufacturing. This term refers to the direct attachment of the image sensor on a circuit board with the electrical connections achieved through wire bonds. In principle, COB is a readily implemented, cost effective and very flexible solution. However, there are issues associated with COB that will become increasingly important in the near future. Particle contamination is the principal issue. In a camera module containing a COB die, the micro lenses are exposed, which puts the pixels at risk of obscuration by particles until the module assembly is complete [Chowdhury, 2006]. The combination of the delicate nature of the micro lenses and their chemical composition effectively precludes standard semiconductor cleaning approaches from being applied. This issue will become more significant as pixel sizes decrease to achieve smaller die and pixel counts (i.e. image resolution) increase in response to market demand. Dirty semiconductor processes such as dicing, die thinning, probe test, die attach and wire bonding, part of the COB-based assembly flow, compound the issue further. It is therefore not surprising that more than 90 percent of defects in COB camera modules, which are not related to manufacturing deficiencies, are due to particle contamination, as can be seen from Figure 5 .


Figure 5: The main defects encountered for a number of manufacturing lots when using COB assembly to build camera modules.

The short-term solution for reducing or avoiding particle contamination is to invest in higher specification clean rooms and more rigorous operator training. However, many solid state camera module manufacturers are already operating in Class 10 environments or better, so there is not a great deal of scope for further improvement at affordable cost. The net effect is the undesirable trend of increased yield loss with increasing sensor resolution and decreasing pixel size.

Next: SHELLCASE CF and wafer-level packaging
The current trend in the image sensor industry is for solutions that protect the delicate micro lenses. Generally, these entail applying a protective glass cover over the imaging area, while leaving the rest of the die exposed so that final assembly and interconnection can proceed in the conventional manner.

SHELLCASE CF
SHELLCASE CF is an example of one such solution. In this process, a glass cover is bonded to the image sensor wafer from the initial stage, so that all of the micro lenses on the wafer are protected from contamination.


Figure 6: Schematic of wafer-level encapsulation of image sensors using a glass cover.

Figure 6 illustrates the formation of cavity frames around each die, forming the contamination-free space over the imaging area. This stage is the key to obtaining high yields independent of the image sensor resolution, pixel size and further processes. Next, the glass is removed from the scribe lanes, leaving the wire bond pads exposed for probing and interconnection. The wafer is then tested to produce maps of electrically good die (known good die, or KGD) and optically good (good optical die, GOD) die. Finally, singulation is performed, resulting in separated die, each with the image sensor area protected by a transparent cover (see Figure 7 ).


Figure 7: Image sensor die with exposed bond pads on all four sides and a glass cover, fabricated using a wafer-level process (SHELLCASE CF).

The elegance of the SHELLCASE CF technology is that the glass cover is applied to the die as a single unit, while the die are still in wafer form. This process is generally referred to as wafer-level packaging. One major advantage of this process is that costs are shared among all the good die on the wafer. For example, for a 200 mm diameter image sensor wafer, which might contain somewhere between 600 and 2000 die, the cost of all the materials, processes and labor to apply the cover glass works out to a few cents per die.

For most imager sensors, the glass cover will be 100µm to 500µm thick. Thinner glass is attractive from an optical standpoint, since light absorption is directly proportional to the glass thickness, as can be seen from Figure 8 . Glass has lower transmissivity than is often presumed and a thick glass plate will degrade the low light performance of a solid state camera module. On the other hand, physically handling 200 mm or 300 mm diameter sheets of glass that are only a few hundred microns in thickness is a highly skilled art. Thus, the cover wafers have to be a certain minimum thickness to attain acceptable process yields.


Figure 8: Transmissivity of light through borosilicate glass as a function of the glass thickness.

Next: Non-optimized silicon design
Non-optimized silicon design
Image sensors are perhaps unique among semiconductor devices in that the die layout is not driven by the need to obtain maximum volumetric efficiency from every last square micron of the wafer area. For normal semiconductors, the die layouts are usually planned to achieve the maximum number of die per wafer, as this minimizes unit die fabrication costs. However, an image sensor is just one of the components required to make a camera module. As can be seen from Figure 4 , other key parts include a lens train, adjustable lens housing, infrared filter, substrate and frequently some passive components, usually decoupling capacitors. A breakdown of the relative costs of these parts for a typical 1.3M pixel camera module is illustrated in Figure 9 . As shown, the cost of the optical parts of a camera module exceeds those of the semiconductor. This means that a compromise has to be struck between the silicon layout and the optical design, with the driving forces being product cost and size.


Figure 9: Relative cost of the key parts of a solid state camera module, normalized to the image sensor die.

First-generation image sensors were generally fabricated following standard semiconductor rules. Optimizing the die layout requires the imaging area to be located close to one corner of the die, so that the electronics blocks can be grouped together efficiently. This is illustrated schematically in plan in Figure 10 and an example of this type of image sensor is shown in Figure 11 .

Figure 10: Image sensor die designed for the most efficient silicon utilization. The optically active area is placed in one corner so the electronics can be grouped together.


Figure 11: The type of image sensor depicted in Figure 10.

To complete the camera module, a lens train will need to be centered over the imaging area (see Figure 12 ). Because the imaging area is located in one corner of the die, the area dimensions of the camera module have to be large in order to accommodate the protrusion of the lens diameter outside of the die area.


Figure 12: A camera module requires a lens train located over the light-sensitive area of the imager. The camera module is therefore much larger than the die in plan.

Now consider a modern image sensor where the die has been inefficiently designed from the point of view of silicon utilization, but where the imaging area is centered in the die. All other factors being equal, the die is actually about 8 percent larger than in the previous case. This time (see Figure 12 and Figure 13 ), the lens train sits neatly over the die, resulting in an overall reduction in the size of the camera module by about 10 percent, by plan area.


Figure 13: Imager with the detector area in the center of the die. Although the silicon die is physically larger than in the previous case, the resulting camera module is smaller.


Figure 14: The type of imager depicted in Figure 13.

Next: Interface considerations

Interface considerations
In addition, efficient silicon designs for normal semiconductors do not take the next-level interface into account. For example, for a fixed number of interconnects, when the bond pads are distributed over fewer die sides, wire bonding is faster. However, this then requires some of the wiring traces on die to be relatively long, which is a source of unreliability and electrical noise. For camera modules where the manufacturing volumes are simply immense, production cycle times are critical. So again, the silicon design tends to be compromised, increasing the die cost, but the premium is more than offset by the reduction in assembly cost.

In the case of image sensors, there is a secondary driver for restricting the bond pads to just two sides, namely the need to incorporate some decoupling capacitors on the substrate as close to the die as possible and inside the housing of the camera module. Inside the camera module, space also has to be set aside to permit the wire bonding tool access to the bond pads and lands. A typical design layout is shown in Figure 15 .


Figure 15: Profile of a typical wire bond used to interconnect a solid state image sensor die, indicating the large space required between the edge of the die and the lens holder to allow for assembly and manufacturing tolerances (drawing units, mm).

The keep out area means that decoupling capacitors cannot be placed close to the die on the sides where there are wire bonds. A more compact design is realized by restricting the bond pads to two sides with the passive components located along the other two sides (see Figure 16 ).

Relationship between cover design and silicon layout
As mentioned, the decision to apply a protective cover over an image sensor die does impact the silicon layout. For instance, the SHELLCASE CF package can accommodate image sensors with wire bonds on one, two, three or four sides. The most efficient and cost-effective arrangement is when the bond pads are placed on two opposing sides, as depicted in Figure 16 .


Figure 16: Imager die with bond pads on two opposite sides allows for passive components to be placed close to the die along the other two sides.

This is also the favored configuration when the camera module has to incorporate passive components, to aid close placement to the die, as described above. The benefit of having wire bonds on just two opposing sides arises from the need to remove the glass cover to expose the bond pads. This operation requires two saw cuts, plus one additional cut to divide the silicon, as illustrated in Figure 17 . On the sides of the die where there are no bond pads, the cover glass and silicon can be cut in a single process, which is faster and less costly to implement.

Figure 17: The bond pads on a SHELLCASE CF die are exposed with three dicing cuts (above), while those sides of the die without bond pads are diced in a single process (below).

Next: Thinner wafers Next: Thinner wafers
For conventional semiconductors, the industry is moving toward ever thinner die. Wafers are now routinely thinned to 75µm thickness, and even 25µm is being practiced in high-volume manufacture. The underlying advances in wafer thinning technology have enabled some of the remarkably slim format products and electronics accessories that are now available. Notable examples are flash memory cards, smart credit cards and the complexity of functionality that can now be crammed into USB devices.

By comparison, CMOS image sensors appear to be stuck in the Dark Ages with die thicknesses of hundreds of microns. There are two good reasons for this. The first is that the depth of black color (i.e. absence of light) that an imager is able to detect is determined by the leakage current of the photodiodes and certain active devices in the imaging array. This property is known as the “dark current” and can be measured. As a general rule, the dark current will increase as the semiconductor wafer thickness diminishes, and hence this metric affects the low light performance of the camera.

The second consideration is mechanical. When the glass cover is attached to the imager, the center region of the die is provided with mechanical reinforcement. This leaves vulnerable protruding ledges where the bond pads are located. If the die is too thin, the fragility of these ledges is reflected in manufacturing yield loss. Fortunately, at the die thicknesses necessary to obtain good dark current performance, the ledges are sufficiently robust to withstand the remaining assembly processes with minimal yield attrition.

Dicing process
Semiconductor wafers obviously must have dicing lanes, also known as streets, from which all the material is removed when the wafer is singulated (see Figure 17 ).

Figure 17: The bond pads on a SHELLCASE CF die are exposed with three dicing cuts (above), while those sides of the die without bond pads are diced in a single process (below). Repeated here for clarity.

Dicing lanes consume valuable silicon acreage, so the impetus is always to minimize street width. The choice of dicing process dictates the narrowness of street with which a silicon wafer can be diced. For exceptionally narrow streets, of the order of 10m or less, laser machining is the favored approach. The amortized capital cost of laser machining is too high for many applications, so the vast majority of semiconductor wafer dicing done today uses diamond saws.

In reality, the process is closer to abrasion than sawing as the blade has no physical teeth. Instead, the blade surface is covered with tiny metal or diamond particles that perform the cutting action. The work area is copiously flooded with lubricant during sawing, so the process is sometimes referred to as slurry sawing.

For this type of abrasive saw blade, there is a relationship between the blade diameter, the depth of cut that can be achieved and the blade width. In this case, not only is the image sensor wafer relatively thick by modern standards, but the thickness of the cover glass needs to be added to the reach of cut needs. Even on the sides of the die where the glass is removed separately to clear the wire bond pads, the saw blade must still possess a reach of over 800m. This means that the minimum street width is around 50µm. The preferred street width is 80µm, as the slight increase in blade thickness pays dividends in terms of the blade stiffness and the maximum feed rate that can be realized.

The cover glass that protects the micro lenses from particulate contamination is attached to the silicon by a picture frame wall of adhesive. The height of the wall is determined by the quality of surface finish that can be obtained for the cover glass. The closer the glass is to the image sensor, the less tolerant the specification can be to imperfections. A tall wall translates directly into a tall component, which is particularly undesirable for image sensors. A good compromise between these conflicting requirements is found to be around 40µm.

The wall width needs to be such that the adhesive joint has sufficient mechanical robustness to survive the rigors of dicing the cover glass, final assembly of the camera module and the operational life of the product. Therefore, a wide wall is generally better. One of the constraints on the wall width is that it must fit between the image sensor area and the wire bond pads, without encroaching on either when assembly tolerances are taken in to consideration. The trend toward CMOS image sensors with ever greater numbers of pixels and sophistication of function, both of which entail additional electronics, means there is ample space on most die for a wall 240µm or more wide (see Figure 18 ). Extensive tests have verified that a SHELLCASE CF wall structure of this width, for example, meets the necessary reliability standards. Manufacturing tolerances require that the design should allow for a 40µm gap between the edge of the pixel array and the inner edge of the cavity wall.


Figure 18: Critical dimensions for the cover glass that must be taken in to account during the silicon layout. Large dimensions will generally ease assembly and improve the product robustness, and must also increase if cover glass is thicker than standard.

Next: Linear separation
Linear separation
Linear separation is the final metric that must be taken into account when designing an image sensor die to accommodate a protective cover glass. Linear separation must exist between the innermost edge of the bond wire pads and the outer most vertical edge of the glass cover. The minimum distance is a function of the type of bonding tool used to join the wire bond to the bond pad.

While tools with deep access and extremely narrow clearances are available, they do not have the same longevity as conventional conical tools. Given the exceptionally high volume in which solid state camera modules are manufactured, this is an important consideration. The cone angle of a workhorse bonding tool is 20 degrees, and the cone needs to clear the full height of the cover glass plus the adhesive wall. In addition to this, sufficient working space is required for the bonding tool. A fully automated wire bonder equipped with a vision system also needs a minimum clear field of view in order to accurately locate the center of each bond pad. For these reasons, the bond pads must be placed no closer than 50µm to the edge of the cover glass.

Conclusion
Millions of solid state image sensors are manufactured each day, most of which are destined for use in portable electronics products. The limitations of current assembly methods make a sensor area protected by a glass cover a very advantageous solution. In order to accommodate the cover glass and permit the optical components of the camera module to be optimally sited, the layout of solid state image sensors is deliberately compromised. Although this increases the cost of the silicon die, because of lower silicon utilization, the approach adds to the net value of the camera module by enabling manufacturers to increase assembly yields and decrease the external dimensions of the component.

About the author
Michael Nystrom serves as senior staff engineer at Tessera, Inc.. He currently focuses on advanced package development, particularly wafer-level packaging and packaging of optical devices. Prior to joining Tessera, Nystrom worked with Agilent Technologies, where he focused on optoelectronics, optical device packaging, and new test and measurement techniques with Agilent Laboratories and the Optical Networking Division. Prior to Agilent, Nystrom spent a little over two years at Candescent Technologies, where he worked on a variety of materials and vacuum project related to the company's field emission flat panel displays. He also had an NRC Fellowship with the National Institute for Standards and Technology, Gaithersburg, Md., where he investigated MEMS-based thin-film oxides as gas sensors. Nystrom holds a bachelor's degree from Carnegie Mellon University's Department of Metallurgical Engineering and Materials Science, and a Ph.D. from Northwestern University's Department of Materials Science and Engineering. Nystrom currently holds 13 issued U.S. patents. He can be reached at .

Giles Humpston, Ph.D. , serves as director, research and development of Tessera, Inc., where he currently focuses on packaging of solid state camera modules and product miniaturization through wafer-level technologies. He has worked extensively in the field of semiconductor packaging, initially for military applications and more recently for high-volume consumer products. Dr. Humpston is a cited inventor on more than 75 patents and has co-authored several text books on metallic joining processes. He has a Ph.D. in alloy phase equilibria and is a metallurgist by profession. He can be reached at .

References
Prismark, 2006. Prismark Semiconductor and Packaging Report Summary, July 2006

Chowdhury, A, 2006. “Camera Module Assembly and Test Challenges”, Semiconductor International, 2/1/2006

Leave a Reply

This site uses Akismet to reduce spam. Learn how your comment data is processed.