This year marks the 30th anniversary of the Linux kernel’s release. Serving as the basis of the open source software movement, the open source code spawned hundreds of projects using free, public Linux distributions. The result has been a lengthy list of robust, stable and flexible products.
Given its success, can the same approach be applied to enabling the adoption of open source hardware? Can an instruction set architecture (ISA) like RISC-V create the basis for the proliferation of open source hardware in the same way that the Linux kernel served as the foundation for open source software?
The answer is both yes and no.
The architecture of the moment, RISC-V is open and available as a standard, allowing freedom, flexibility and speed in building products around it. But the flip side is that hardware is more complex, and with multiple layers in the stack, this means it’s not as simple as shipping a software package.
We polled stakeholders in the RISC-V hardware ecosystem — OpenHW Group, RISC-V International, NXP Semiconductors and Andes Technology. We examine the similarities to open source software, barriers to adoption of open source hardware and the significance of a support community and ecosystem.
Finally, we consider: What does open source hardware mean for commercial chip makers?
Quality, support ecosystem are key
Rick O’Connor, president and CEO of the OpenHW Group, equates RISC-V with the Linux kernel “The RISC-V ISA is really what the kernel was for Linux at the beginning, and other open source software projects and initiatives sprung up as a result,” O’Connor told EE Times. “Certainly, the kernel was the seed on the software side 20 years ago, and the ISA is that same seed, I think, on the hardware side.”
Still, barriers remain to entry in adopting open source hardware. “Certainly, one of them is quality,” O’Connor added. “For example, if you work in a high-volume chip or SoC [system-on-chip] company, you’re not going to walk into your boss’s office and bet your badge on this IP block that you downloaded and say ‘We’re ready to go’ based on this cool core from a university, and we should put it in our high volume SoC.’”
Hence, the group advocates an open verification flow “that people can use and see the quality and the results that the ecosystem has achieved, [then] produce what would be expected by a high-volume SoC company if they were doing it totally on their own,” said O’Connor.
The group also notes industry misconceptions about RISC-V and the role of the RISC-V International, the foundation that oversees the core ISA specification.
“People always thought that the foundation was about developing cores,” O’Connor said. “It’s not. It’s about developing a series of specifications defining the instruction set architecture. And then there’s all kinds of different adoption options: commercial, open source, closed source, for profit, non-profit, written in different languages, depending on what your favorite logic capture language is.”
In that respect, he emphasized the OpenHW Group is not just about RISC-V cores. “What we are really focused on is developing the artifacts needed for heterogenous cluster computing that can be used in different sizes of SoCs. Clustering different types of cores, accelerators, and all the various blocks that we need.”
This is where the RISC-V ISA has played a key role, unleashing “a new frontier in innovation,” O’Connor asserts. “It’s made it accessible for anyone to stitch a core together, no agreements to sign with anybody. Download the ISA specs and away we go. From that standpoint it’s been a key enabler. If you cast your mind back to 20 years ago, there were many, many, implementations of the Linux kernel—far more than we have today.
“Our challenge for the hardware industry is how do we get to the five or six families of cores implementations around RISC-V that will be sustainable.”
Rob Oshana, vice president of software engineering for R&D at NXP Semiconductors, suggests open source hardware will evolve in much the same way as has open software. “Linux is actual source code that thousands of developers use and contribute to in a collaborative way” via the Linux Kernel Archives.
“RISC-V International owns a specification, not an implementation. This specification evolved in a very collaborative way and it’s been proven to work given the current state of the RISC-V community and ecosystem,” Oshana said.
“Because the foundation does not own an open implementation, OpenHW Group is filling that void with the charter to develop free, open, royalty-free implementation[s], plus other collateral just like Linux Foundation.”
Needed: Community support, not just a spec
With the expansion of open source from software to hardware, there is a growing need for community or partner ecosystem involvement. “Any open community requires nurturing, care and feeding. Throwing something into a Git and calling it ‘open’ always fails. A community is needed,” Oshana argued.
“OpenHW Group cores would not be successful if it was not for efforts of the community to build cores, boards, software, reference platforms.” OpenHW Group “is leveraging best practices to make this hardware technology successful as well,” he added.
The key is leveraging best practices and “investing real engineering at a sustained rate to make and keep [hardware development] successful,” Oshana argued. “Each distribution will be unique in some ways.”
Meanwhile, open source tools continue to evolve. “We need a reliable set of hardware-based tools to support this over time,” Oshana noted. He and others suggest the true measure of an open community is the level of engagement. For example, once an implementation is released, a key metric is how the user community manages change requests, bug fixes and the like. “This is the equivalent of the upstreaming process in Linux,” Oshana said. “The role of maintainer needs to be clear.”
This community aspect is also reinforced by Mark Himelstein, chief technology officer at RISC-V International. “Linux was not necessarily the best OS, but why did people adopt it? Because there’s a community and support. The magic was the pride of ownership. It’s now a no-brainer to use Linux, and with RISC-V, I think we are the Linux of hardware. I believe in five to ten years’ time RISC-V will similarly be a no-brainer for hardware.”
Hardware tougher then software
Open source hardware and software differ primarily in terms of complexity throughout the stack. “Look at the majority of the volume of the silicon in production today—more than 95 percent of that volume was produced and verified in a Verilog-based tool flow and commercial verification infrastructure for that production release,” O’Connor said. “So, if we want someone to adopt the cores, they need to be easily stitched into that commercial tool flow.”
SoC vendors mostly use SystemVerilog Universal Verification Methodology verification environment. “We are not going to try to teach or convince them to use something different,” said O’Connor. “If we really want RTL adoption of these open source blocks, they need to be able to drop into that tool flow.”
Still, the physics of hardware presents problems not faced by software developers. “Right from the physics at the geometry level in the semiconductor fabs, the recipe behind that fab process,” notes O’Connor, who cites work in areas like process design at larger nodes as encouraging.
“You’ve got the recipe in the fab, the libraries on top of that, the physical layer of those CAD tools to produce GDSII and the mask technology itself; and then the equipment to produce masks, and the simulation and verification software and tools that you use to validate your design, the synthesis tools you use to capture and synthesize your design, and then the IP that goes into those designs,” he explained.
“All of those layers in that stack have deep patent portfolios associated with every layer, developed over decades. And there’s so much linkage between each of those layers. So, trying to replace the whole stack right out of the gate with open source implementations and tools is not something any commercial company is going to try to do,” O’Connor noted.
The founders of the OpenHW Group considered whether to create an ecosystem geared specifically toward RISC-V cores. They ultimately decided not to.
O’Connor said their first goal was to create those cores. “But we are doing it with a view and mindset of a vision around solving open source hardware implementation challenges. In other words, make it easy to build heterogenous clusters with common building blocks, and your ability to tailor it with your own secret sauce—accelerators and extensions built around it.”
That involves collaborating on the common elements and defining an interface point at the software tools level, at the hardware RTL level, and even at the verification level. “Your value-add is then how you modify that common set of building blocks to add custom acceleration, build these custom heterogenous clusters that implement your secret accelerator algorithm. So, the notion is that RISC-V as an ISA lets us get started on compelling common building blocks at the processor core level, and then build on that. All the while leveraging the best commercial tools to deliver high confidence to the implementers.
“So, the IP is something they can trust.”
He predicts open source FPGAs will soon emerge, and eventually SoCs.
Andes Technology is an example of how a commercial company plugs into open source infrastructure. The Taiwanese company has launched several RISC-V based processors, with a number of announced customer implementations.
In addition to designing in its RISC-V cores for SK Telecom and Renesas, Andes recently announced that EdgeQ, a startup developing a 5G base station chips, will use its core RISC-V license with an Andes custom extension to deliver an open and programable 5G platform with integrated AI. The custom extension would allow EdgeQ to design, extend, and customize their own instruction sets to achieve novel performance, features and power profiles which they claim are unmet by current wireless infrastructure.
“RISC-V for us is an open source ISA for the hardware interface or description, not an open source core,” said Frankwell Lin, president of Andes Technology. “In the RISC-V camp, from company to company, we are competitors. We cooperate at the level of RISC-V standards. However, in the day-to-day business, we have to compete with each other.”
Andes touts a decade of experience with embedded RISC cores as well as a proprietary ISA architecture. “Although we moved 90 percent of our resources to RISC-V development, we still have our proprietary core, doing license business, and both still work,” Lin said.
Besides RISC-V, Lin noted the growing amounts of open and industry standard hardware components. “In hardware, RISC-V is not the first one being open source.” For example, the Verilog hardware description format is open source, largely by agreement between EDA leaders Cadence and Synopsys, Lin said.
Also open are hardware interface standards such as PCIe, USB, OpenCL and OpenCV as well as Bluetooth and WiFi for connectivity.
As the roster of open hardware tools grows, a key question is whether a foundation akin to the Linux kernel is needed to spur adoption of open source hardware. As with Linux, community support and individual company contributions are crucial.
Still, heavy investments in design tools and production gear make open source hardware a tough sell. Those hurdles mean hardware blocks must be easily integrated with existing tool chains in order to address the far greater complexity at each layer of hardware design and production.
>> This article was originally published on our sister site, EE Times.
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