This article discusses the disconnect between the digital design engineer's vision of bus structures on the printed circuit board (PCB) and the failure of tools to capture and route this vision in an efficient manner. Around the globe, there are many different electronic system design flows and roles.
This article assumes a design flow that may or may not match the flow and roles of your organization, yet the solutions discussed fit into any flow. The first part of this two-part article follows the capture of Intellectual Property (IP), by the design engineer and collaboration of this IP throughout the remaining design flow. The second part of this article focuses on the PCB designer collaboration of the IP through the remaining design flow.
While designing and capturing the logic, the design engineer has envisioned the bus structure and its relationship among the components. This envisioned structure is considered IP, typically a valuable asset to their organization. The problem is capturing and sharing this IP.
Often, design engineers attempt to capture and communicate IP in a hand drawn document or on a paper napkin. While many aspects of EDA are in fact automated, this process has not had effective tool support. A hand drawing on a napkin has been the most efficient to date.
1. The napkin shows an example of a typical Engineering sketch of a bus structure.
While quick to capture, the napkin may or may not physically map to the PCB. This is a problem because of size issues, such as width of the physical bus, mechanical parameters of the card, physical size and pin outs of components. Therefore, the original IP may be completely invalid because it is physically impossible to follow; EDA tools must not only replace, but also improve upon the napkin. They must effectively capture the IP and communicate accurate, usable/reusable IP throughout the design process.
When the IP is accurately captured, collaboration is required throughout the remaining design flow. Effective collaboration shortens the design timeframe by preventing the re-entry of IP by others. Additionally, by using the exact IP, the original intent is maintained. Errors and misunderstandings are removed with effective collaboration with the results being increased efficiency in the design flow.
What is needed is a topology planning tool. This tool should allow the design engineer to define and capture the bus structure and effectively communicate it throughout the design flow. To effectively plan bus structures, they first must be logically defined. Bus definitions can come forward from captured logic in the schematic or ASCII input, depending on the design flow. With buses defined, a card outline, components and board stackup, the design is ready for accurate capture of the topology.
The tools to capture topology must be easy to use, flexible and accurate while providing useful visual feedback. This should start with a true, exact physical representation of bus paths. A 64-bit bus must truly represent the width of 64 parallel traces and 63 trace-to-trace clearances, all while understanding impedance implications per layer. Also, as buses are drawn on different layers, they need to be visually represented on these layers. The purpose of all this is to ensure what the design engineer is capturing actually fits into the sections of the PCB where they're intended to, otherwise the integrity of the IP is in jeopardy.
2. The “P” in the bus path represents a packed bus, meaning; the routed traces are as compressed as possible and follow these paths, on the specified layers.
Design engineers must have flexibility when creating their IP and they should be able to draw their bus paths with a few key components placed, all components placed or no components placed. A topology planning tool should aid in the creation process by providing flexibility, not force a procedure.
Since the placement of components affects the bus structure and vice versa, efficient topology planning must support the placement of components by buses. During placement, designers should be able to filter and place those components that share a bus. As illustrated in Figure 3 , the selection of a bus should filter the component list to include components associated to the selected bus.
3. U1002 is being placed from bus PCI2. Note the netlines render to a PCI2 bus path and component pins.
Typically, when placing components, net lines span between component pins and aid in placing (Figure 4a ). This provides a useful purpose, real-time feedback of component connections to associated components. Yet, as more components are placed, more net lines are brought into the display. For complex designs, the density, overlapping and twisting of net lines can cause more confusion than guidance.
4. The two parts of the figure show a general flow of interconnects between components. Effective topology planning tools must provide a better understanding of relationship between buses and their components, by showing Netlines funneling into Bus Paths.
From Figure 4 , both displays are useful while capturing IP. Yet the evolved image in figure 4b shows the organization and visual benefit brought through topology planning. Net lines are bundled in their layer specific paths, showing accurate space requirements. The results are a clear representation of bus to component relationships while understanding scale. As they draw their bus paths, design engineers create order in the placement and are able to visually see and dictate how the bus is routed and components placed.
Bus paths mayaccommodate any count of bits up to thetotal defined in the bus. This providesgreat flexibility in planning the busstructures. For example, while drawing a64-bit bus the decision was made to split itinto two 32-bit paths and put them ondifferent layers. At any point, these buspaths can be merged into a larger bus path,or further reduced to smaller bit countbuses.
5. Topology Planning and Routing willsupport complex structures.
To continue the example, one of the 32-bitbus paths was split into two 16-bit paths asshown in figure 6 . This was done toefficiently connect to a Ball Grid Array(BGA) component package shown in the upperleft hand side of figure 5 .
6. You can split of a 32-bit bus intotwo 16 bits bus paths. On the right youcan see the topology routing results.
Topology planning must include optionalabilities to capture complex bus structuresto include:
- Layer changes with via patterns
- V and T splits
- Netlines spanning from the sides of bus paths
- Overlapping paths of same bus
- Netline assignments with bit ordering
While flexible, a “packed” bus structuredoes not work with all topology planningscenarios. If, for example, there are twoBGAs close together and sharing a 64-bitbus, there may not be enough room for apacked bus path. In this scenario it isbetter to go with an unpacked area for thebus. An unpacked area doesn't dictate apacked structure. Instead, it specifieslayers, layer bias per selected layer andarea for the selected bus bits to route. Thedesign engineer is still capturing IP, yetwith an area border, layers and layer bias.
Timing concerns create signal delays thatcan consume vast amounts of trace space on aPCB. Rather than being surprised to wherethey'll fit, it's best to estimate theneeded space and plan where tune delaylengths will be added.
A good topology planning tool provides thiscapability, where it's needed during theplanning stage ” allowing the designengineer to specify areas on the PCB tolocate the delay lengths. Planning ahead ofthe process ensures the needed space isavailable. Optionally, a plan should havethe ability to manage and specify the areafor signal delay traces.
Planning for Signal Integrity
With ever increasing signal frequencies, itis crucial to consider signal integrityduring topology planning. Planning forsignal integrity includes insuring againstcrosstalk, parallelism and planning forreturn signal path. Typical design flowsfind signal integrity problems after mosttraces are routed and the design almostcomplete.
Depending on the signal integrity problem,the solution may require space betweensignals traces, or a ground shield betweenthe two signal traces or a ground/voltageplane clear of obstacles. Yet the PCB designis almost complete and may have high tracedensity in the area of the PCB where theproblems are occurring. This is the wrongtime in the design cycle to be informed ofsignal integrity problems because there maynot be enough physical space to easily solvethe problem.
Topology planning is the right time to planfor signal integrity; before traces arecommitted to the PCB. Rather than trying tofind space after the interconnects arecompleted, it is better to plan for a returnpath, prevent crosstalk and parallelismbefore trace routing is started. Otherwise,the necessary space for a plane layer,spacer or ground shielding may beunavailable. If planned for, instead ofreacting to signal integrity issues, thedesign cycle is further shorten byanticipating these potential problems earlyand necessary signal performance isachieved.
When IP is captured, it is time to share itthrough collaboration. Seamlessly, thedesign engineer captured IP shouldcollaborate and drive the placement ofremaining component and routing of traces.The second part of this two part articlewill discuss the PCB designer role and usageof topology planning and topology tracerouting.
Dean Wiltshire is a Product Architect,in the System Design Division of MentorGraphics Corporation. His article has been also published on EETimes