LONDON Cavium Networks CNS3XXX family of single and dual core ARM SoC processors include integrated hardware accelerators and a range of I/Os for glueless voice, video and data connectivity.
Power management techniques enable operation to start below 1 Watt and the family is targeted for applications including fiber to the home (FTTH) broadband gateways, network attached storage appliances, multimedia picture frames, media and print servers, IP cameras and wireless access points.
The devices are based on superscalar, ARM11 MPCore processors operating at up to 700MHz, each with 32KB I-cache, 32KB D-cache and a 256KB L2 cache to provide over 1400 Dhrystone MIPS (DMIPS).
Each processor comes with instruction set extensions for digital signal processing (DSP) and media processing, and integrates a vector floating point unit (VFP) and memory management unit (MMU).
The cores also incorporate Jazelle technology from ARM that enhances the performance of Java applets running on the CNS3XXX family. The high performance cores combined with large caches deliver non-blocking, wire-speed performance for voice, video and data applications.
DSP extensions on the ARM11 MPCore processors drive enhanced voice applications including support for wideband codecs, DECT and advanced call control features such as conferencing.
Included in over 10 application acceleration engines are a packet switch for wire-speed switching, hardware-based NAT and QoS engine, TCP offload, packet processing ngine (PPE) for wire-speed packet processing, content inspection engine for L7 application processing and filtering, RAID 5/6 XOR engine, 2D graphics engine with an integrated LCD controller, and a security engine for IPSec, SSL, intrusion prevention and anti-virus processing.
High-bandwidth, low-latency integrated memory, system and networking interfaces includean intelligent x16/x32-bit, 800MHz DDR2 memory controller, three Ethernet MAC interfaces supporting RGMII/GMII/ MII, Dual USB2.0 / SATA2 / PCIe – all with integrated PHYs, TDM/PCM, LCD interface, SDIO, Camera Interface and a host of system interfaces including GPIO, SPI, UART, I2S and I2C.
An integrated power management unit (PMU) provides multiple power-saving modes during operation including wake-on-LAN support, dynamic control of CPU power per core, automatic shut down of logic that is not operational and other modes for a total of six different power saving profiles. On-chip voltage regulators assist the effectiveness of this PMU and power consumption ranges from under 1 watt for the single core version to less than 2.5 watts for the highest end dual-core version.
The ECONA CNS3XXX software development kit (SDK) builds upon the existing OCTEON and OCTEON Plus SDK and includes Linux SMP, GNU Toolchain, Simple Executive for fast path applications, performance tools, simulator, APIs for hardware acceleration and a set of reference applications.
The ECONA CNS3XXX processor family offers core clock speeds ranging from 300MHz to 700MHz with single- and dual-core configurations. Package options range from 27mm x 27mm and 15mm x 15mm ball grid array package to lead quad flat pack.
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