Cavium unveils 48-core, 2.5GHz OCTEON III MIPS64 CPU family -

Cavium unveils 48-core, 2.5GHz OCTEON III MIPS64 CPU family


Cavium, Inc. has just released a  family of OCTEON III MIPS64 multicore SoCs with anywhere from 1 – 48 cores that can deliver over 100Gbps of application performance per chip.

Designed to allow for linear scaling across multiple chips in a fully coherent fashion, the 2.5GHz OCTEON III processors, said Syed Ali, President and CEO at Cavium, provide the most compute power of any standards-based communications processor chip, at an unmatched 120GHz of 64-bit compute processing per chip.

The company expects that OCTEON III will deliver up to 4X higher application performance than the earlier OCTEON II with significantly superior performance per watt. Ali said the OCTEON III is the industry’s first SoC to integrate best-in-class high-performance search processing leveraged from Cavium’s NEURON Search processors along with market-leading 5th generation DPI Acceleration, dramatically reducing BOM cost and power.

“Providers of Next-Generation Networks are being challenged to handle the explosive increase in traffic because of the fast adoption of cloud technology and mobile broadband, as well as increased exchange of multimedia and video rich content,” he said. “Higher traffic coupled with the need for intelligent application-aware and secure processing has shifted the bottleneck for L3 – L7 data and security services to CPU processing that requires an unprecedented level of 64-bit CPU GHz processing power and dedicated hardware acceleration.”

He pointed out that according to the Cisco Visual Networking Index (VNI), by the end of 2015, annual global IP traffic will increase four-fold from 2010, reaching 966 Exabytes per year and mobile traffic will increase 26-fold.

Additionally, said Ali, “The Internet of Things or Devices” is growing rapidly. According to GSMA, he said, the global mobile industry trade group, and other analysts, the number of internet connected devices will increase from 9 billion in 2011 to over 20 billion by 2020, and could potentially reach 50 billion, accelerating the migration to IPv6 and generating massive amounts of data traffic.

With up to 48 superscalar MIPS64 cores, operating at up to 2.5GHz. Cavium’s third generation custom cnMIPS “Real Cores” include core-architecture enhancements, larger caches and short, efficient pipelines to deliver lower-latency, greater determinism and superior performance/watt than alternative “Pseudo-Core” solutions.

A new 20+ Tbps HyperConnect provides high-performance access to a large, highly associative L2 cache running at full core-frequency which results in OCTEON III delivering substantially lower latency for packet processing when compared to three level cache architectures that typically operate at a fraction of core-frequency.

He said the use of a low latency coherency architecture enables multi socket designs, allowing multiple OCTEON III chips to appear as a single logical high-performance processor with up to 384 cores, providing up to 960GHz compute, up to 800+ Gbps of application performance and up to 2 Terabytes of memory capacity at a dramatically lower latency versus alternative solutions.

Traffic arriving at any chip can be processed by any other chip, without the data first having to be written to the local memory of the first chip, which enables superior throughput and lower latency.

The new processor family has the ability to handle over 500Gbps of I/O connectivity per chip, over a variety of interfaces including multiple ports of 40G, 20G, 10G, GE, Interlaken, Interlaken/LA, SRIO, PCIe Gen3, SATA 6G and USB 3.0.

The SDK for the new OCTEON III hardened APIs and software stacks for a variety of networking, security and storage applications, with support for standard operating systems, GNU tool-chains, C/C++ based software applications, advanced debugging/profiling tools such as Oprofile, Valgrind, Cachegrind and production quality APIs and software stacks.

Hardware design collateral is available now. First 28nm OCTEON III silicon is expected to sample in the second half of 2012. Please contact your Cavium representative for additional details.

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