Celoxica ships HyperTransport solution - Embedded.com

Celoxica ships HyperTransport solution

CAMPBELL, Calif — Celoxica has developed a complete off-the-shelf hardware and software compiler design bundle for high-Performance computing (HPC) using industry standard HyperTransport (HTX) slots. The HTX bundle combines an intellectual property (IP) core for HTX compliant connectivity, an FPGA-based HTX acceleration card and a comprehensive software-programming environment.

Celoxica (Abingdon, Enngland) is a member of the HyperTransport Technology Consortium, and the RCHTX acceleration card includes two Xilinx Virtex 4 FPGA devices, 24 Mbyte of dedicated QDR SRAM, and a range of I/O.

The main co-processor FPGA is a high density 16 million gate device that can be reprogrammed by the user to accelerate compute intensive algorithms. The second FPGA is configured as a bridge, containing an HTX IP core developed and licensed by Celoxica. This bridge FPGA and IP provide the HyperTransport interconnect between the FPGA co-processor and the entire host processor system and memory space.

Celoxica’s DK Design Suite provides an IDE and compiler for software programming of the FPGA co-processor. DK allows HPC programmers to use familiar software languages and legacy code in the development of hardware accelerators. Celoxica’s technology compiles high-level, C-based code directly to the user FPGA device, eliminating the need to recode complex and proprietary algorithms into a low level hardware description language. A board support package (BSP) and software API is provided for the RCHTX card.

The low latency, high bandwidth interconnect provided by HyperTransport coupled with Celoxica’s software programming environment for FPGA hardware enables HPC programmers to exploit FPGAs as parallel co-processors that deliver orders of magnitude higher performance with little or no impact on existing power and floor space budgets.

Celoxica’s HyperTransport solution complements its existing Accelerated Computing products, which provide compiler and hardware interface support to enable FPGA-based co-processing for a wide range of HPC solutions.

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