CEVA, Inc. has just taken the wraps off a suite of advanced processor and multicore technologies to further enhance its CEVA-XC DSP architecture framework for high performance wireless applications.
Targeting such designs as wireless terminals, small cells, access points, metro and macro base-stations, the new enhancements it has added are comprehensive multicore features, high-throughput vector floating-point processing and a complete set of coprocessor engines offering power-efficient hardware-software partitioning.
According to Eran Briman, vice president of marketing at CEVA, MUST is a cache-based multicore system technology with advanced support for cache coherency, resource sharing and data management.
Initially available for the CEVA-XC, it supports the integration of multiple CEVA-XC DSP cores in a symmetric multiprocessing or asymmetric multiprocessing system architecture, along with a broad range of technologies designed specifically for multicore DSP processing. These technologies include:
- Dynamic scheduling using shared pools of tasks,
- Hardware event based scheduling defined via software,
- Task and data driven shared resource management,
- Advanced memory hierarchy support with full cache coherency,
- Advanced automated data traffic management without software intervention, and
- Special prioritization scheme based on task-awareness.
To aid in the design of advanced multi-core SoCs containing ARM processors and multiple CEVA DSPs, Briman said, CEVA has added extensive support to the CEVA-XC architecture framework for the ARM AXI4 interconnect protocol and AMBA 4 ACE cache coherency extensions.
The improvements have the aim, he said, of simplifying software development and debugging process for SoC designs, while also reducing the software cache management overhead, processor cycles and external memory bandwidth.
CEVA has also incorporated support for floating-point operations to the CEVA-XC vector processor unit, in addition to the traditional fixed-point capabilities to support the needs of designs based on LTE-Advanced and 802.11ac standards based on multiple input multiple output (MIMO) processing, where the system utilizes multiple antennae to transmit and receive data.
Floating point operations are supported on full vector elements, processing up to 32 floating-point operations in every core cycle to meet the performance requirements of even the most demanding wireless infrastructure applications.
In addition to these enhancements, CEVA has also incorporated a dedicated instruction set architecture (ISA) for high-dimension MIMO, including support for 802.11ac 4×4 use cases.
To further optimize advanced wireless systems for low power and performance, said Briman, the company has introduced a comprehensive set of tightly-coupled extension (TCE) coprocessor units.
These coprocessors address functions of the modem where greater performance can be achieved through the use of hardware that is tightly coupled with the CEVA-XC. The TCEs now include:
- Maximum Likelihood MIMO Detectors (MLD),
- 3G de-spreader units,
- FFT with NCO phase correction,
- HARQ combining, and
- LLR compression / de-compression.
He said these tightly-coupled extensions are complemented by a unique automated low-latency data traffic management scheme between the DSP memory and the coprocessors to minimize DSP intervention and enable a truly parallel co-processing capability.
These TCEs are part of fully integrated and optimized modem reference architectures for licensees targeting user equipment, infrastructure and Wi-Fi applications.