Chip Path Design Systems debuts free online web-based FPGA/SoC design - Embedded.com

Chip Path Design Systems debuts free online web-based FPGA/SoC design

Aiming to turn complex system on chip and FPGA development into more of a high level “cut-and-paste” process Chip Path Design Systems has just gone on line with its vendor neutral portal for design, comparison and purchase of System-on-chip IP blocks and FPGA parts.

Announced at the 2014 Design Automation Conference this week, the new service makes available what it calls is the industry's first device-mapping tools and IP directory for FPGA front-end design with free and pay by credit card use models.

“As FPGAs have embraced the latest 28nm nodes much faster than ASICs or ASSPs, they have increasingly become a competitive solution for box, board, and systems designers,” said J. George Janac, CEO of Chip Path Design Systems.

To simplify and speed up the process of evaluating and designing such systems, he said, the company has has aggregated 6,000 intellectual property (IP) cores from over 400 vendors for use in FPGA mapping and estimation.

The result is the ability to significantly reduce design costs and speed design time by providing technical and business information in one graphical and easy-to-use system. The portal features devices from Altera Corp., Lattice Semiconductor Corp., Microsemi Corp. (Actel), Xilinx Inc. and Achronix.

Over 29 FPGA families are supported, representing 430 bases with over 2,000 package combinations and over 11,000 part numbers and speed grades. Real-time inventory and part number purchasing can be done directly from the website, linking distributors such as Arrow, Avnet, Digi-Key, Mouser and others.

To improve FPGA efficiency, said Jenac, the trend has been to hard diffuse large SoC-style blocks alongside the more expensive FPGA fabric. The FPASSP (Field Programmable ASSP) represents a hybrid of the flexibility of an FPGA with embedded ASSP hard-diffused partitions.

To simplify such designs, using the ChipPath serice, architects can design chips using semantic or placeholder IP, directly using vendor IP or their own internal IP to create, assemble and test economic viability of their designs.

He said ChipPath can map pure FPGA devices as well as those with complex SoC style partitions. Currently Chip Path's FPASSP portal supports SmartFusion, SmartFusion 2, Zynq-7000, Arria V SE/SX and Arria 10 SE/SX.

The company's ChipArchitect tool uses built-in semantic models and can generate over 1.8M end-to-end I/O channel and core models with either a hard embedded IP or FPGA fabric implementation. Additional tools allow the addition of blocks either directly from an external vendor IP catalog or from an internal IP catalog. Pre-RTL blocks can be defined using LUT, BRAM, DSP and other resources. ChipArchitect provides a complete array of input options and outputs the best choices of devices across the industry for its customers.

“FPGA Search can be run from a single form with as little as six resource numbers,” said Janac. “Chip Path search tools also offer the option to import vendor synthesis and mapping results allowing development board-based RTL designs to be mapped onto much cheaper devices for production.

The Chip Path FPGA portal has a free use starter model. The FPGA search tool and IP directory can be used free of charge without a login, allowing mapping of devices and IP directory search. Free use of the FPGA ChipArchitect tool is also provided, but login is required.

A $79/year membership provides added device access to 28nm FPGA devices as well as new 40nm/65nm devices from Lattice Semiconductor and Microsemi. Full FPGA package selection, SERDES mapping, speed grade analysis, real-time inventory and distributor ordering start at $199/week. A similar package that adds FPASSP devices is $299/week. In addition, 20nm/22nm pre-production device models are directly available from Chip Path for a monthly subscription fee.

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