Chip verification goes on-line - Embedded.com

Chip verification goes on-line

HAIFA, Israel – IBM Haifa Laboratory's recently established Engineering & Technology Services (E&TS) facility has developed key parts of a Web portal that will provide access to select tools to chip designers and verification engineers on an as-need basis.

Engineers will no longer need to purchase, house or maintain the latest computer systems and software for chip design and formal verification, they can access these capabilities from IBM as a service. One of the first users is Israel's Technion University, a chip design and verification facility that has customers worldwide.

Students at the university's VLSI (very large system integration) design lab can securely sign in and gain access to this IBM Web portal, and once inside the portal, hosted in New Jersey, access tools that help them with the design of the chip and formal verification, the process of mathematically proving that every circuit in the chip, no matter how complicated, works according to its specifications.

The tools support the industry-standard language PSL for requirements specification, which is based on IBM's Sugar 2.0 language. PSL has been recently selected as an industry standard by the Accellera EDA standards organization. The service gives engineers a choice, enabling them to collaborate from a Web browser on Unix, Linux, or a Windows platform. Using web conferencing, they can design with other users to debug and fix design problems in real time. All communications between the client and server are completely secure and there is a mechanism to protect sessions from network instability.

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