DDR memory is becoming more widely used becausenearly all applications requiring fast processing of huge amount of data – desktop computers, servers, gaming consoles, portable consumer devices for example – depend on the fast access to, and availability of, large amounts of high bandwidth RAM.
Its characteristics allow volatile information to be held and can beaccessed in a faster and more direct way which is critical for highspeed and efficiency that are demanded by computer systems today. Youcan see from the chart in Figure 1below that the evolvement of the DRAM with the speed and datatransfer rate getting faster.
|Figure1. Over the years, CPU clock rate has experienced an exponential growthand this has fuelled the clock rate growth for RAM memories.|
DDR RAM allows for data to be fetched on both the rising and fallingedges of the clock, thus doubling the effective transfer rate of theclock. This is in contrast to the older SDR SDRAM which makes a datafetch on only one edge of the clock cycle.
For example, a 100-MHz DDR clock would achieve a peak transfer rateequal to that of a 200-MHz clock. This is what the DDR1 technology canaccomplish, and the speed of which can go up to 400MHz. As can be seenfrom the diagram, we now have the latest standard called DDR3 whichbrings the data rate speed up to 1.6Gbps.
Besides the well known PC applications, DDR memories are widely usedin high speed and memory demanding embedded applications such as:graphic cards, Blade servers, networking devices and communicationdevices.
One area of market segment that critically demands both speed andlower operating voltages is the portable consumer world. For instance,we are seeing more and more electronic gadgets that provides forgraphics and motion pictures (video) capability which fuels the highdemand for more DRAM memories.
Products such as Gaming systems like PSP (Play station portable),Smart phones, Digital cameras, or GPS devices (global positioningservice) would all contain some type of DRAMs, and would all need thetotal power consumption to be kept as low as possible in order for thebattery to run longer.
The DDR Memory Standards
The main differences between the DDR1, DDR2 and DDR3 SDRAM, are shown in Table 1 below:
|Table1. DDR(1), DDR2, and DDR3 comparison|
Putting the operating clock frequency or speed aside, from theoperating power point of view, we can see that DDR1, DDR2 and DDR3memories are powered up with supply voltages of 2.5, 1.8 and 1.5Vrespectively.
Thus producing less heat and providing more efficiency in power thannormal SDRAM chipsets which use 3.3 V. DDR3 uses less power than DDR2by operating at 1.5V – a 16.3% reduction compared to DDR2 (which is1.8V).
Both DDR2 and DDR3 memories have power saving features such assmaller page sizes and an active power down mode. Furthermore, DDRmemory interface uses the new stub series-termination-logic (SSTL)topology, which aims to improves noise immunity, increases power-supplyrejection, and reduces power dissipation (for comparable speeds) due toa lower-voltage rail.
One more point worth noting is that DDR3 and DDR2 SDRAM support ondie termination, while DDR1 SDRAM does not support this.
These features and power consumption advantages make them especiallysuitable for use in notebook computers, servers, and low power mobileapplications.The main difference between SDRAM and the current in-useof DDR SDRAM are:
* Power supply voltage
* Data transfer Frequency
For power supply voltages, DDR SDRAM system requires three powersupply sources. They are VDDQ, VTT and VREF as shown in the Table 2 below .
|Table2. Comparison of SDRAM VDDQ, VTT and VREF|
Although DDR memory doubles the data-transfer rate without doublingthe clock rate, avoiding pc-board design and layout complexity, itmandates the DDR regulators to have tighter dc regulation, highercurrents and close tracking for both the termination supply voltage(VTT) and memory bus supply voltage (VDD).
The new stub series-termination-logic (SSTL) topology was introducedto improve noise immunity, increases power-supply rejection, andreduces power dissipation for a lower-voltage rail.
JEDEC Standards JESD8-9A (for SSTL_2) and JESD 8-15 (for SSTL_18)define the VDDQ, VTT, and VREF, as well as driver/receiverspecifications to meet noise margins at VDDQ = 2.5 V (for DDR1) andVDDQ = 1.8 V (for DDR2), respectively. Now, let's look at thisinterface more closely to understand the needs of VREF and VTT.
The SSTL Interface
Shown in Figure 2 below is thenew stub series-termination-logic (SSTL) topology of DDR memory. Theinterface of SSTL_2 has the following features:
1. DDR memory has apush-pull output buffer, while the input receiver is a differentialstage requiring a reference bias midpoint, VREF. Therefore, it requiresan input voltage termination capable of sourcing as well as sinkingcurrent.
2. Between any output bufferfrom the driving chipset and the corresponding input receiver on thememory module, we must terminate a routing trace or stub withresistors.
|Figure2. The stub series-termination-logic (SSTL) topology of DDR memory.|
The current flow direction of the VTT power source change as thestate of the bus change. Thus, the power source of VTT need both sinkcurrent and source current as illustrated in Figure 3 below , with the red andblue arrows.
|Figure3. When output of the controller ' H ' being,: Sink (electric currentsinking as red arrow). When ' L ' being,: Source (electric currentsourcing out as blue arrow).|
Since the VTT supply must sink and source current at ½ VDDQ,a standard switching power supply cannot be used without a shunt toallow for the supply to sink current.
Furthermore, as each data line is connected to VTT with relativelylow impedance, the supply must be extremely stable. Any noise on thissupply can go directly on to the data lines.
The bus signal swings across VTT voltage around the center. When thebus signal voltage exceeds the threshold voltage of the comparator, itwill output an inverted image of the signal.
In this system, the threshold voltage of the comparator is the VREFvoltage provided by the power supply source. As there is hysteresis inthe comparator, the image of the signal will have a time shift.
Connecting the DDR System bus
In Figure 4 below there is anexample of how the DDR bus is connected for a typical DDR2 system. Inthe memory application example depicted below, the VTT for the data busis generated within the memory via ODT (on die termination) by VDDQ.However, it is still necessary to supply VTT from power source IC tothe address bus control signal.
For DDR2 memory, the terminal resistances for data bus are built-in,but terminal resistance for the address bus control signal is stillneeded as in the case of DDR1 memory. VTT supply is derived from thepower supply chip ” that is marked as MC34716.
|Figure4. In DDR2 applications, VTT for the data bus is generated insidememory via ODT by VDDQ. However, it is necessary to supply VTT frompower source IC in the address bus control signal.|
Note when the conductor length of the address bus control signalbetween the controller and the memory is sufficiently short (forexample below 63.5mm); the terminal resistance is not needed andconsequently no VTT supply is required.
Power supply considerations
In choosing a good DDR power supply, one must weigh the costs withperformances as well as other technical requirements like inputvoltages or output currents. Assuming that the electrical specificationis already fixed, the choices of DDR Powers IC's are primarily weightedon the following factors:-
1. What power conversion efficiency can the DDR supply ICoffer? Most vendors provide efficiency at least 90% and above. Higherefficiency translates to less loss and would mean a great deal toprecious power sources coming from batteries in portable products.
2. Is the switchingfrequency sufficiently high? Higher frequency means smaller valueexternal inductor and capacitors can be used and would be smaller insize.
3. Does the supply ICprovides sink and source capability and voltage tracking feature thatare specifics to drive DDR memory?
4. Package size of the chipplays an important factor to space constrained applications likeportable consumer products.
5. Are there extensivecontrols and interface that can offer the designer the flexibility ofmany control and protection functions? This would allow for easyimplementation of complex designs.
In Figure 5 below is anapplication example using a single chip DDR memory power managementchip with two power channels which generate VDDQ, VTT and VREF.
|Figure5. A single chip DDR memory solution|
Note that the power supply is not dependent on a DDR memory powersupply. The SW1 will provide the DDR memory power supply (VDDQ). It isalso connected to the terminals VREFIN and PVIN2 on MC34716.
Terminal SW2, from MC34716 supplies the VTT Voltage for the memorychip data bus, and tracks VDDQ to achieve 1/2 VDDQ. Pin VREFOUT isdirectly connected to VREF of DDR memory, supplying a stable referencevoltage of 1/2 VDDQ. Terminals /SHTD, /STBY and /PGOOD are used tointerface with the MCU to control the DDR Chipset with the help of aDDR memory controller.
Norman K W Chan is a marketing manager, and W. S. Wong is asystem engineer at from Freescale Semiconductor.