Codasip adopts Imperas for RISC-V processor verification - Embedded.com

Codasip adopts Imperas for RISC-V processor verification

Codasip has included Imperas golden reference models in its DV testbenches to ensure an efficient verification flow that accommodates a wide range of flexible features and options while scaling across the entire roadmap of future cores.

Codasip has adopted Imperas reference designs and the Imperas DV solution for Codasip intellectual property (IP). Codasip has included Imperas golden reference models in its DV testbenches to ensure an efficient verification flow that accommodates a wide range of flexible features and options while scaling across the entire roadmap of future cores to enable rigorous confirmation of functional quality.

RISC-V is a modular architecture that offers many different permutations of base instructions, standard optional extensions and custom instructions. This often raises concerns about implementations and the risk of fragmentation. Codasip’s internal testing already uses an internal instruction-accurate model, several sources of direct and random testing (internal and externally provided), and several different technologies to check and ensure processor compliance. Imperas configurable reference models are already fully tested and enable all the configuration options needed to support this comprehensive view.

The Codasip engineering team based in Sophia-Antipolis, France, reviewed the challenges of the evolving RISC-V specifications, the full Codasip processor IP portfolio, extensions and configurable features, plus future roadmap plans. Imperas solutions were chosen as they were the most suitable to support the operational workload and scale requirements. The Codasip engineering team set up the infrastructure and test frameworks around the Imperas RISC-V reference models to efficiently test all configurations with the ability to adapt for new roadmap features.

Philippe Luc, verification director at Codasip, commented, “While processor verification is not a new problem, there are many RISC-V suppliers, with customization and various levels of verification or conformance: customers are legitimately concerned about both quality and fragmentation.” He added that using Imperas was an important part of its quality process, which extends Codasip’s differentiation. “The Imperas independence, reputation and technical strength provides our customers with further reassurance in our ‘best in class’ RISC-V processors,”

Simon Davidmann, CEO at Imperas Software Ltd, said, “Codasip provides the RISC-V market with a range of processor solutions that enable optimized performance for a wide range of applications. Design verification of this processor IP is fundamental to Codasip continuing to deliver the highest-quality processors as it moves to the next generation of its IP. Each additional optional feature roughly doubles the verification workload. The Imperas approach supports Codasip’s development by applying continuous integration/continuous development to a sophisticated processor DV environment by using simulation and offers an efficiency advantage without compromising optional features. Imperas and Codasip share a common vision that improved quality is essential to the success of RISC-V.”

The Imperas RISC-V reference models for Codasip are available now to lead customers and partners for software development and as a foundation for virtual platforms. Codasip and Imperas will be at the RISC-V Summit, co-located with DAC for 2021, December 6-8 in San Francisco, CA (U.S.).


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