EnSilica and Evatronix SA have collaborated to develop the eSi-RISC processor SoC which includes USB 1.1, 2.0 and 3.0 connectivity.
The collaboration with Evatronix (Bielsko-Biala, Poland) is seen as adding an important building block to EnSilica’s (Wokingham, UK) strategy of providing eSi-RISC processor sub-systems complete with integrated peripherals. The collaboration also broadens the Evatronix USB IP sub-system portfolio with RISC processor combinations.
EnSilica has integrated the Evatronix USB 1.1, 2.0 and 3.0 IP solutions, including support for USB OTG, into its eSi-SoC Generator tool, which automatically produces processor sub-system RTL including bus arbitration enabling USB SoC-based solutions to be generated for customers by EnSilica’s development team.
Support can be provided for low speed, full speed, high speed and superspeed devices which support data rates up to 5Gb/s.
The configurable Evatronix IP allows hardware resources to be optimized to include parameters like the number of end-points and options dedicated for USB DMA engine support. Suspend and resume power management functions are supported reducing the overall system power.
A fully featured USB software stack, with mass storage class option, provides everything required to deploy a low-cost USB processor sub-system reducing risk, cost and time to market for customers.
As well as the USB IP, a set of eSi-Connect peripherals are available for integration with EnSilica’s eSi-RISC processors. They include cache and static memory interfaces through to peripherals such as I2C, UART, SPI, a Smartcard (ISO7816-3) interface, Ethernet, RTC, system timers, DMA and encryption accelerators.
The eSi-SoC Generator supports either single or multi-processor architectures with a mixture of AMBA APB, AHB or AXI based buses. The SoC architecture and eSi-RISC processor configuration is described by an XML format file. Each eSi-RISC processor can be configured separately within the XML file with over 50 configuration options available for each processor. These include the base 16-bit or 32-bit data word support, memory architecture, addressing modes and extension instructions such as load multiple, bit field extraction, single cycle multiply and multi-cycle divide. This allows each processor to be optimized for the end application reducing silicon resources and minimizing the overall system power.