Collaboration to generate interface PHY IP for use on 28-nm - Embedded.com

Collaboration to generate interface PHY IP for use on 28-nm

Synopsys Inc. and  GlobalFoundries Inc. have agreed to collaborate on the development of a DesignWare interface PHY IP for use on a 28-nanometer process.

The two companies have a long standing relationship which has resulted in the development of DesignWare PHY IP from 180nm to 32nm process technologies.

They are the first to announce the development of USB, PCI Express, DDR, HDMI, SATA and XAUI PHY IP targeting 28nm process technologies with scalability to future generations.

The SuperSpeed USB (3.0), USB 2.0, HDMI 1.4 Tx and Rx, DDR3/2, PCI Express 2.0 and 1.1, SATA 1.5/3 Gbps and 6 Gbps, and XAUI  PHY IP will be used with or GlobalFoundries 28 nm 'Gate First' High-k Metal Gate (HKMG) process technologies. The collaboration should enable mutual customers to differentiate 28-nm designs.

The two companies have a long standing relationship which has resulted in the development of DesignWare PHY IP from 180nm to 32nm process technologies. They are the first to announce the development of USB, PCI Express, DDR, HDMI, SATA and XAUI PHY IP targeting 28nm process technologies with scalability to future generations.
 
DesignWare PHY IP solutions target a broad range of high performance, ultra low power mobile and consumer applications, where the key requirements include minimal area and low dynamic and leakage power consumption. The PHY IP is designed to tolerate process, voltage and temperature variations and supports multiple power management features.
 
Front end design views for the DesignWare PHY IP supporting GlobalFoundries 28nm process technologies are available now. Initial design kits and DesignWare PHY IP  are scheduled for availability in Q1 of 2011. Additional products will be released throughout 2011.

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