Configurable DSP core fits IoT, wearables -

Configurable DSP core fits IoT, wearables

Everyone is talking about the Internet of Things (IoT) these days. Consumers are eager to be tempted with the latest and greatest IoT products; design houses are furiously beavering away creating these products; and microcontroller and DSP vendors are constantly announcing higher-performance, higher-capacity, lower-power next-generation devices that are targeted at the IoT domain.

One problem is that it's not possible to create a one-size-fits-all IoT processor. Different IoT devices have varying requirements for three ubiquitous functions:

  • Sensing: Always-on sensor fusion involving navigation, context awareness, embedded speech and embedded vision, biometric monitoring (voice and face recognition/triggering), etc. 
  • Computation: Bit manipulation, security and encryption, digital signal processing, etc. 
  • Communications: MAC and PHY, Bluetooth Low Energy, Wi-Fi, ZigBee, SmartGrid, LTE, GNSS, etc.

And, sitting on top of all of this we also have control functions. The thing is that every application has its own unique requirements, and existing processor cores are not ideally suited for all of these tasks.

And so we come to Tensilica, which (since April 2015) is now a business unit of Cadence Design Systems. Tensilica has a very interesting backstory. Founded in 1997, the Tensilica team came up with a very clever tool called the Xtensa Innovation Platform, which can be used to generate custom dataplane processor unit (DPU) cores that offer a unique blend of CPU plus DSP functionality.

Using Xtensa, system architects can describe the architecture they require for a particular application, ranging from an ultra-small, low-power, cache-less controller to a high-performance 16-way SIMD, 3-issue VLIW DSP core. You can employ Xtensa to generate DPUs that are unique in two basic ways:

  • Configurability: Xtensa offers a menu of checkbox and drop-down options allowing you to pick and choose only the features you need. Once you've determined the best implementation, the automated Xtensa Processor Generator creates pre-verified RTL and a complete matching software toolchain (C/C++ compiler, debuggers, simulators, and RTOSes), including models for system integration and EDA scripts for production.  
  • Extensibility: You can add your own instructions, registers, register files, and much more using the Tensilica Instruction Extension (TIE) methodology. In this case, you only have to specify the functional behavior of the new data path elements in the Verilog-like TIE language, and then the RTL and whole tool chain is automatically generated.

It's wonderful to have all of these configuration possibilities at one's fingertips. The trick, of course, involves knowing which buttons to press and which options to select in order to achieve the optimal DPU for a particular application space. This explains why, in 2006, Tensilica used its own Xtensa technology to introduce what it called the “Diamond Standard” family of processor cores. This was (and still is) a set of six off-the-shelf synthesizable cores that range from area-efficient, low-power controllers to high-performance DSPs (Digital Signal Processors), all of which lead the industry in their respective categories both in lowest power and highest performance.

The end result is that the Cadence Tensilica Xtensa architecture is now the second most popular licensable processor architecture in the world, shipping at a rate of over 2B cores per year in products spanning sensors to supercomputers.

All of which brings us to today's announcement of the Cadence Tensilica Fusion DSP core.

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