Configuring a logic analyzer
Logic analyzers (Figure 14 ) are used extensively in the electronic industry to analyze the digital circuit’s functionality. Logic analyzers evaluate the functionality of the circuit by generating all combinations of inputs and analyzing the corresponding outputs from the digital circuitry.
If the digital circuit of interest consists of only combinational logic then the user has to provide the number of inputs and outputs present in the digital circuit. Logic analyzer functionality implemented in the PSoC will generate all combinations of inputs possible and captures the output from the digital circuits. The input Vs output for all combinations is displayed on the GLCD.
The steps to activate the logic analyzer functionality of the kit and the operations performed are as follows:
- Select the LOGIC ANALYZER to enable the functionality (Figure 15 ).
Figure 15: Selection screen for Logic Analyzer
- Select between the Combination or Sequential circuit for analysis (Figure 16 ).
Figure 16: Screen to select Combinational or Sequential Circuit
- Select the number of inputs (max of 3) and number of outputs (max of 2). (Figure 17 )
- The CPU processes the number of input combinations and generates all possible input combinations and stores in an array.
- The CPU sends out the different input combinations to the input pins of the external digital circuit and simultaneously reads the output pins of the digital circuit.
- The waveforms are displayed on the GLCD (Figure 18 ).
Since the sequential logic circuits have outputs which depend on present and previous inputs, input from the user is requested. Generating the inputs from the CPU will be less efficient since the present output is affected not only by the present input but also by previous outputs. PSoC will obtain the number of inputs and outputs present in the sequential circuit. User will enter the input data.
The clock is generated from the PSoC and it is assumed that data given by user is valid, i.e. no set up time or hold time violations. The clock is generated by the PSoC such that input data is valid, i.e. each datum will start in the middle of negative level and end at the middle of next negative level of the clock.
Hence, at the rising edge of the clock data is valid and proper sequential operation will be done. Working is similar to that of combinational circuit, but here the clock is also given by the PSoC and output is sampled at the rising edge of the clock.
Configuring a function generator
Function generators/signal generators are used to generate different types of waveforms that are of varied frequency and amplitude. In the kit, the function generator (Figure 19 ) is implemented using the DAC to generate triangular and sine waves, using Clock/PWM to generate Square wave.
The RAM holds the lookup table containing data for the sinusoidal and triangular wave generation. The DMA transfers the data from RAM to DAC without CPU intervention. The DAC will generate the desired voltage levels corresponding to the data transferred to it by the DMA.
The rate of output will determine the frequency of the triangular/sinusoidal wave generated. The clock to DAC and DMA is changed in accordance with the user frequency. The sine or triangular wave is built with 16 samples per cycle for higher frequency (1 KHz 62.5 kHz), 32 samples per cycle for medium frequency (100-999Hz), and 256 samples per cycle for low frequency (1-99Hz).
The selection of different numbers of samples for different frequencies serves two purposes:
- At low frequency a better resolution is obtained (otherwise at low frequency steps for samples will be seen, which is not desired),
- The same clock can be used for all frequencies because frequency of the waveform is varied by dividing the clock. If there are fewer samples per cycle there will be a lower limit of frequency up to which clock can be divided, and increasing the samples per cycle will decrease the lower limit of frequency that can be generated using the same clock.
The user of the kit can enter into function generator mode by selecting the FG in the Menu (Figure 20 ). After than the developer will be asked for frequency selection (Figure 21 ), and wave type (Figure 22 ). The function generator will then display that selection on the CRO for the following: sine wave (Figure 23 ), triangular wave (Figure 24 ), and square wave (Figure 25 ).
Figure 21: Interface to select frequency (5500Hz)
Figure 22: Interface to select wave type
Figure 23: Sine wave display on CRO
Figure 24: Triangular wave display on CRO
Figure 25: Square wave display on CRO
FFT (Fast Fourier Transform) is an important tool in the oscilloscopes. It is the frequency domain representation of the signal. A 256 point firmware Radix-2 FFT (Butterfly technique) is used in the current FFT implementation. The sampling rate shall be adjusted by the user to get the required accuracy. Shown in the figures below are the kit displays for selecting the FFTs for a 1.67 kHz sine wave (Figure 26 ), a 20 kHz sine wave (Figure 27 ) and a 68 KHz sine wave (Figure 28 ). Shown in Figure 29 are the various waveform displays on the PSoC-based electronic lab kit.
Figure 27: FFT of 20 KHz Sine Wave (Sampling Frequency is 144.44 KHz)
Figure 28: FFT of 68 KHz Sine Wave (Sampling Frequency is 144.44 KHz)
Figure 29: Various waveform displays on SoC based electronic lab kit
In summary, the PSoC was used to configure the following feature set in a handheld electronic lab kit:
- Voltage and Time scalable Oscilloscope with Autoset and Turbo display feature.
- Easy resistive touch user interface.
- FFT display of the input signal (Hence the oscilloscope serves both time and frequency domain signal realization).
- A Logic Analyzer to analyze the combinational and sequential digital circuits.
- A Function Generator feature to generate necessary test signals.
Achuth Rao MV is an Applications Engineer at Cypress Semiconductor. He holds a Bachelor’s Degree in Electronics and Communication Engineering from RV College of Engineering, Bangalore. His interests include signal processing and building touch sense solutions. He can be reached at .
Anush M Shet is currently working as an Applications Engineer at Cypress Semiconductor. He holds a Bachelor’s Degree in Electronics and Communication Engineering from RV College of Engineering, Bangalore. His interests lie in the area of Analog Circuit Design and SoC based designs . He can be reached at .
Sachin M Dhareshwar works as an Applications Engineer at Cypress Semiconductor. He holds a Bachelor’s Degree in Electronics and Communication Engineering from RV College of Engineering, Bangalore. He enjoys building Analog and Mixed signal designs. He can be reached at firstname.lastname@example.org .