CoolRunnerII uses FZP all-digital core - Embedded.com

CoolRunnerII uses FZP all-digital core

Xilinx's CoolRunner-II RealDigital CPLDs have an all-digital core. They are available in densities ranging from 32 to 512 macrocells, and provides a performance up to 300MHz and pin-to-pin delays as fast as 3.5ns while providing a standby current of less than 100A.

The CoolRunner-II second generation Fast Zero Power (FZP) design technology uses a 0.18 process and 1.8V core voltage.

The all-digital core designed with FZP process technology provides a scalable process that will allow continued geometry shrinks for future cost optimisation, greater density and performance, and lower power consumption.

The advanced I/O solution consists of both the physical interface and the protocols to maximise system interface bandwidth. The CPLDs provide clock management features that enable a total clock management solution.

CoolCLOCK clock management is a combination clock divider and clock doubler that divides the incoming clock by two and then doubles the clock at the output level to maintain the same performance while reducing the internal power consumption.

The CoolRunner-II family is supported by Xilinx free ISE WebPACK and WebFITTER internet based design software. With Xilinx WebPACK software designers get a no cost fully functional, downloadable desktop solution with HDL and ABEL synthesis and simulation capability.

Xilinx WebFITTER internet based design software gives designers free CPLD design fitting tools to evaluate designs using CoolRunner-II and all Xilinx CPLD families.

In addition to free web-based software, Xilinx offers the 4.1i Integrated Software Environment (ISE) software tool series. ISE 4.1i includes ProActive Timing Closure technology and integration with some EDA tools for advanced logic design.

The XC2C64 (64 macrocell) device is available now with the five other device densities becoming available over the next two quarters.


Published in Embedded Systems (Europe) February 2002

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