HoustonVMETRO, Inc. has introduced a serial FPDP (Front Panel Data Port) core that targets Xilinx Inc.'s Virtex-II Pro FPGAs used in applications that include signal processing, high-speed data recording, real-time imaging, and test systems that rely on the FPDP interface.
The serial FPDP core, offered as intellectual property (IP), fully complies with ANSI 17.1-2003 and establishes a point-to-point data link with a choice of data 1.0625-, 2.125-, or 2.5-Gbits/sec. FPGA Rocket IO connections when using suitable host FPGA cards. With the help of fiber optic transceivers, a serial FPDP data link can extend up to 10 km.
For design flexibility, the FPDP core accommodates all operating modes, including unidirectional links, bidirectional links with data flow control, copy mode, and copy-loop mode. Thus it allows for multiple end points that ease such tasks as the simultaneous recording and processing of raw data.
The core requires a minimum footprint within an FPGA, for example occupying about one percent of an XC2VP70, leaving much of the FPGA available for other circuits even when several FPDP cores are used in one device.
The serial PFDP IP core comes in an EDIF format suitable for simulation. The core can be implemented on such VMETRO FPGA products as the PMC-FPGA03/03F, VPF1, and 3CPF1 line of air- and conduction-cooled models; on a customer's FPGA hardware; or, subject to license conditions, on non-VMETRO-based FPGA products.
The serial FPDP core sells for $6,000 and is available now.
VMETRO, Inc. , 1-281-584-0728, www.vmetro.com