Cortus low-power 32-bit core targets IoT apps - Embedded.com

Cortus low-power 32-bit core targets IoT apps

Cortus has launched the first of a new family of products based on its v2 instruction set. The APS23 is the first product to use the v2 instruction set and is aimed at low power, always on/always listening systems and those with less demanding clock frequencies such as Bluetooth Smart. The APS23 core was built to deliver a new level of efficiency, ease of integration and cost of ownership for low-power, connected intelligent devices. The core reduces embedded system power by optimizing the size of the instruction memory.

The APS23 has a Harvard architecture, sixteen 32-bit registers, a 3-stage pipeline and a sequential multiplier. It supports the AXI4-Lite bus as well as Cortus APS peripherals. The core delivers 2.83 DMIPS/MHz and 1.44 CoreMarks/MHz in computational performance. The minimal usable APS23 CPU starts around 9.8 kgates when optimised for area. Dynamic power is 12 microwatts/MHz with a 90 nm process (Cortus cores are synthesisable and foundry independent).

The Cortus v2 instruction set allows the seamless mixing of 16-, 24- and 32-bit instructions without mode switching. This instruction set is richer than the v1 instruction set which used a mix of 16- and 32-bit instructions. Cortus will continue to offer products based on the v1 instruction set (e.g. APS3R) in parallel with the new cores based on the v2 instruction set. All C/C++ or assembler code developed for the v1 cores can be used unmodified on the v2 cores.

All cores interface to Cortus’ peripherals including Ethernet 10/100 MAC, USB 2.0 Device and USB 2.0 OTG via the efficient APS bus. They also share the simple vectored interrupt structure, which ensures rapid, real time interrupt response, with low software overhead.

The APS tool chain and IDE (for C and C++) is available to licensees free of charge, and can be customized and branded for final customer use. Ports of various RTOSs are available such as FreeRTOS, Micrium µC/OSII.

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