Cost-conscious Blackfin packs in the processing power -

Cost-conscious Blackfin packs in the processing power


Analog Devices Inc. has released an entry-level Blackfin DSP that cuts down on the package size and price while providing 800 million multiply-accumulates per second/400 MHz of performance.

Featuring active power draw down to 88 mW and a 9 x 9-mm, 64-lead lead-frame chip-scale package (LFCSP), the Blackfin BF592, at $3 in 10k quantities , is aimed at making high-performance digital signal processing available for power-constrained and small-form-factor applications in the industrial, medical, video, audio and general-purpose markets.
Target applications for the BF592 include portable medical products; audio devices; imaging products, such as CMOS-sensor-based 2-D bar code scanners; and smart metering products in smart grid applications.

Using the 800 MMACs or 400-MHz clock speed, the Blackfin BF592 provides the ability to run more-sophisticated algorithms.

The system peripherals include a watchdog timer; three 32-bit timers/counters with PWM support; two dual-channel, full-duplex synchronous serial ports (SPORTs); two serial peripheral interface (SPI)-compatible ports; one UART with IrDA support; a parallel peripheral interface (PPI); and a two-wire interface (TWI) controller.
A factory-programmed instruction ROM block contains the VDK RTOS and C run-time libraries, which include core DSP algorithms (FFTs, filters, vector, matrix, statistical functions), a floating-point emulation library, and compiler support routines (integer division, conversion from integral to floating-point and vice versa). Also included are functions for fract16, 32-bit floating-point and 64-bit floating-point types and functions to support the fractional complex type, as well ETSI and C run-time functions.

An on-chip L1 instruction ROM on the ADSP-BF592 may be customized to contain user code with 64 kbytes of L1 Instruction ROM available for custom code and the ability to restrict access to all or specific segments of the on-chip ROM.

One application sector particularly identified by ADI is to use the Blackfin BF-592 as the processor for smart meter software-designed radio (SDR). It has capability to support the physical layer in software and less than 50 percent MIPS loading for orthogonal frequency-division multiplexing (OFDM) schemes supporting 800-kbit/second data rates. Estimates show 160 MHz out of 400-MHz needed for operation and less than 50 percent of on-chip RAM used for the OFDM scheme.

ADI believes that 8 kbytes of data RAM and 8 to 16 kbytes of instruction RAM needed with surplus processing and memory can be used for additional functionality, including additional demodulation processing for improved performance under adverse channel conditions. The BF-592 peripherals support transceiver and host processor interfaces and the parallel port interface (PPI) used for interface to the radio transceiver.

A 2-MHz channel bandwidth requires 4 million samples/second of I&Q data, and the PPI supports a peak rate up to 40 million samples/s. Operation at 800 kbits/second will require less than 5 percent of the SPORTs bandwidth, and the SPI is used for booting and for control messages passed to and from a host. No external memory or glue logic is required.

The EZ-KIT Lite evaluation kit for the Blackfin BF592 DSP includes an evaluation suite of ADI’s VisualDSP++ development environment with the C/C++ compiler, assembler and linker. ADI also has a Blackfin emulator, which provides a comprehensive development platform.

The EZ-KIT Lite evaluation kit is available from authorized distributors at $199.

A data sheet is available for download.

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