Cost-effective SoCs are the key to fostering innovation -

Cost-effective SoCs are the key to fostering innovation

Innovation is being stifled by the lack of options for chip design implementation. Innovation entails trying the unknown. It's an evolutionary process in which something new is tested, then refined as market preferences become clear.

Innovative products are not purchased by mass markets. They're purchased by early adopters, which represent a tiny fraction of the total population. It doesn't make sense to commit millions of dollars and hundreds of thousands of ICs to an evolving product. In the current environment, it's impossible to fund such a risky enterprise.

The risk of a large up front financial investment is completely overcome by FPGAs, but the tradeoff is performance degradation, power consumption, and high unit costs. FPGAs are cheap if you buy 100,000 of them, but in quantities of 10,000 units, a 200,000-gate FPGA can cost $30, in addition to about $3 for the microcontroller. That $33 price tag contributes about $132 to the price of the end product. High prices threaten product adoption.

At the other extreme are e-beam ASICS. Unlike FPGAs, they have performance and power-consumption specs that are comparable to those of full-custom ASICs. Like FPGAs, they have no masks charges, but each chip is created through factory electron beam programming. However, they aren't really a “no-NRE” proposition.

Although there are no mask-charges for e-beam ASICs, there are license fees for the IP. License fees for an ARM core, an AHB bus, and an APB bus can easily run $100,000 per design. What the innovating company doesn't pay in mask fees is taken up by license fees. In addition, unit costs for e-beam devices are even higher than for FPGAs. In 10,000-unit quantities, an e-beam device costs between $100 to $200 per unit. Amortizing the license fees increases the unit cost to $110 to $210 per unit. Add $440 to $640 to the price of the end-product and the pool of early adopters will shrink accordingly.

The optimal solution would be to keep NRE charges low enough to minimize the financial risk of innovation, while offering unit costs that foster early adoption. Second-generation metal- programmable cell fabric (MPCF-II) technology keeps unit costs low by offering silicon densities comparable to those of full-custom standard-cell ASICs. Customizable MCUs implemented in this technology are 85% standard product MCUs, with no license fees. The remaining 15% of the die is available for customization.

Because most the chip is pre-defined, it can be configured and routed using only three metallization and three via layers, thereby reducing the number of masks from to six and cutting total NRE costs to $75,000. Since there are no license fees for the ARM core, buses or other IP, the fixed investment is about 30% less than that required for a no-NRE e-beam ASIC.

The silicon efficiency of the underlying MPCF technology supports unit pricing of only $10 in quantities as low as 10,000 units and $5.50 each at 50,000 units. After fully amortizing the NRE charge, the total unit cost is $17.50 for 10,000 units and $7 for 50,000 units. Power consumption is 98% less and performance is about 8X better than the FPGA solution.

The only way to foster continued innovation is to give fabless IC companies a chance to develop and market-test leading-edge products cost-effectively, in volumes that correspond to the size of the early adopter population. Reducing the silicon portion of the end-product price from over $100 to $40 or $60 will increase the chances of early adoption and help to continue the cycle of innovation.

About the author
Jay Johnson has over 22 years experience in the semiconductor industry. He is responsible for new product and IP roadmaps, tactical and strategic marketing, marketing communications, public relations, and product management for Atmel's ASIC and ASSP product line in North America. Johnson received his BSEE degree from Kansas State University and his MBA from the University of Phoenix. He can be reached at .

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