Cryo-CMOS IP enables qubit control chips at cryogenic temperatures -

Cryo-CMOS IP enables qubit control chips at cryogenic temperatures

sureCore is developing a CMOS IP library suitable for operation at extremely low temperatures required for quantum computing applications, enabling design of cryo-CMOS control chips co-located with qubits in a cryostat.

One of the biggest challenges in the scaling of quantum computing applications is the need for cabling to connect qubits operating at low temperatures with the control electronics most of which is only specified for operation down to – 40° C.

To address this, low power embedded intellectual property (IP) specialist sureCore has said it is developing a range of CMOS IP suitable for operation at the extremely low temperature required for quantum computing applications. This will enable the design of Cryo-CMOS control chips that can be co-located with the qubits in the cryostat.

This will help solve the current problem of extensive and performance limiting cabling used to connect the qubits with their associated control electronics usually running at room temperatures outside the cryostat. For quantum computers to realize their potential, thousands, if not millions of qubits will be needed, and they must be kept at cryogenic temperatures to ensure correct operation. Currently, the major barrier to scaling is the amount of control cabling, which is in direct proportion to the number of qubits within the system. This problem can only be solved by moving the control electronics into the cryostat.

In its announcement, sureCore outlined the two key challenges and how it is aiming to address this with its cryo-CMOS IP.

The first challenge is the current the standard industrial operating temperature range. For most commercial CMOS process technologies this is specified from -40°C to 125°C and this is reflected in the transistor SPICE models supplied by silicon foundries. By working closely with both industry partners and foundries, sureCore said it plans to design and characterize silicon IP capable of operation down to 4°K.

Paul Wells - sureCore
Paul Wells

The second challenge is to ensure that the control electronics dissipates as little heat as possible so as to minimize the cooling load on the cryostat. Hence it is critical that, as far as is possible, low power design techniques are deployed. The CEO of sureCore, Paul Wells, said, “We are experts in reducing the power consumption of CMOS; our design methodologies have already demonstrated up to 50% dynamic power reduction in embedded memory IP. By deploying these techniques in the design of cryo-CMOS, we aim to minimize the excess heat generated thereby easing the scalability challenges for large quantum computers.”

The company already has silicon-proven, ultra-low power, embedded memory IP that it will customize for this cryo application and will be launched as its CryoMem range. Using the knowledge gained from the development of CryoMem, sureCore plans to create a range of IP tailored for the development of complete quantum computing control electronics in cryo-CMOS. It aims to offer a complete portfolio of cryo-IP for licensing by companies wishing to develop cryogenic control ICs.

Wells added, “This new IP library will help unlock the potential of quantum computing by accelerating the development of cost effective, cryogenic control ASICs for the hundreds of quantum computing companies out there competing to deliver competitive quantum compute solutions.”

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