Cyclone FPGAs for high volume use - Embedded.com

Cyclone FPGAs for high volume use

The Cyclone family of FPGAs are based on a new architecture thathas been created from the ground up to provide the industry's lowestcost FPGA family. Altera believes the family will be used in highvolume systems in the consumer, communications, industrial, andautomotive markets providing access to the benefits of programmablelogic devices at ASIC prices.

The Cyclone family was developed using the same product definitionprocess that yielded the Stratix device family (Embedded Systems,April 2002 page 15. Customers where consulted to get the mostappropriate mix of price, density, features and performance. Thisprocess yielded devices four times the density of the previouslow-cost FPGAs with a 60% die size reduction over previousarchitectures.

FPGAs have historically found their sweet spot in high-bandwidth,high-performance applications where end products cost thousands ofdollars. High-volume applications have traditionally used ASICs fortheir cost effectiveness.

However, the economics of designing ASICs &endash; the high-costof non-recurring engineering (NRE) charges and the uncertainly ofend-market success &endash; are rapidly favouring programmable logic.FPGAs have the advantage of being off-the-shelf customisable productsthat require no up-front costs and no minimum order quantities(MOQ).

A 32bit Nios microprocessor and peripherals configuration consumesless than 1,400 logic elements (LEs) and delivers 50Dhrystone MIPS(DMIPS). It will take up less than half the smallest density Cyclonedevice, which costs $4.

A single Cyclone device with multiple Nios embedded processors canreduce costs without sacrificing system performance.

Cyclone devices are available with densities from 2,910 to 20,060logic elements (240,000 logic gates and over 1 million system gates)and up to 288Kbits of RAM.

Dedicated memory interface circuitry is used to seamlesslycommunicate with double data rate (DDR) SDRAM and FCRAM devices aswell as single data rate (SDR) SDRAM devices at up to 266Mbits/s.

The FPGAs support a variety of single-ended I/O standards foroff-chip data transmission, including LVTLL, LVCMOS, PCI, SSTL-2, andSSTL-3. For designers requiring faster data rates and more robustsignal transmission capabilities, Cyclone devices provide up to 129low voltage differential signalling (LVDS) compatible channels, eachcapable of up to 311Mbits/s performance.

The embedded memory structure consists of columns of 4608bitmemory blocks. Each block supports multiple configurations, includingtrue dual-port and single-port RAM, ROM and FIFO buffers.

For clock management, eight low=skew, global clock networks spanthe device fed by four dedicated input clock pins. Phase-locked loops(PLLs), each with three output taps provide frequency synthesis andphase shifting capabilities for complete system clock management on-and off-chip.

Altera has also developed a serial configuration device familythat is designed to cost that is less than 10% of the price of theFPGA itself. The 1Mbit EPCS1 and 4Mbit EPCS4, are available in 8pinsmall outline SOIC packages. Any unused memory in these devices canbe used for general purpose storage such as storing the software codefor Nios embedded processors. Circuit designs, which includemicrocontrollers and Flash memory, could alternatively use these forconfiguration.

Design software support for the Cyclone device family is providedby Quartus II software version 2.1 or the free Quartus II Web Editionsoftware for full design, synthesis, place-and-route, andverification capabilities supporting the Cyclone device family.


Processor cores ready-for-use

The Embedded Processor Portfolio from Altera is a collection ofmore than 100 embedded processor intellectual property (IP) cores fortypical microcontroller and embedded processor applications.Developers can design and ship systems with the cores without payingany license or royalty fees.

The Portfolio supports Altera's Cyclone device family and, sayAltera, in high-volume applications, a 32bit Nios processor in aCyclone device is less expensive than most discrete 32bitmicroprocessors available today.

Based on the Nios soft-core processor architecture and Red Hat'sGNUPro Toolkit, the Portfolio provides a development environment. ThePortfolio of cores can also be used with select members of Altera'sStratix device family and Excalibur embedded processor solutions.

The Embedded Processor Portfolio CD-ROM also includes the free webedition of the Quartus II development software, the SOPC Buildersystem development tool, and the OpenCore Plus evaluation version ofthe Nios embedded processor.

Published in Embedded Systems (Europe) October 2002

Leave a Reply

This site uses Akismet to reduce spam. Learn how your comment data is processed.