Cypress announces PSoC 4 architecture for ARM Cortex-M0 devices -

Cypress announces PSoC 4 architecture for ARM Cortex-M0 devices

The PSoC 4 programmable system-on-chip architecture from Cypress Semiconductor Corp. combines Cypress’s PSoC analog and digital fabric and CapSense capacitive touch technology with ARM’s power-efficient Cortex-M0 core. The scalable architecture delivers access to dozens of free PSoC Components (“virtual chips”) represented by icons in Cypress’s PSoC Creator integrated design environment. The new PSoC 4 device class will challenge proprietary 8-bit and 16-bit microcontrollers (MCUs), along with other 32-bit devices.

The PSoC 4 architecture enhances Cypress’s CapSense capacitive-touch sensing technology by offering significant improvement in noise immunity. In addition to capacitive sensing, PSoC 4 targets field-oriented control (FOC) motor control, temperature sensing, security access, portable medical, and many other applications.

The PSoC 4 architecture offers power leakage of 150 nA while retaining SRAM memory, programmable logic, and the ability to wake up from an interrupt. In stop mode, it consumes only 20 nA while maintaining wake-up capability. Cypress claims it has the widest operating voltage range of any Cortex-M0-based device, enabling full analog and digital operation from 1.71V to 5.5V. The architecture facilitates integrated, high-performance custom signal chains and provides both configurable analog and flexible routing. PSoC 4 leverages the PSoC Creator integrated design environment.

According to Cypress, PSoC solutions bring the flash-based equivalent of a field-programmable ASIC to embedded designs without lead-time or NRE penalties. PSoC integrates configurable analog and digital circuits with an on-chip microcontroller, reducing component count and simplifying revisions. A single PSoC device can integrate as many as 100 peripheral functions, accelerating cycle time and improving quality while reducing board space, power consumption, and system cost.

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1 thought on “Cypress announces PSoC 4 architecture for ARM Cortex-M0 devices

  1. What is the fundamental difference between PSOC4 and PSOC5? Looks like 4 lacks the extensive analog programmable block; I imagine it'll be their entry level 'us too' ARM

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