DAC 2022: Digital twins and the door to the metaverse - embedded.com

DAC 2022: Digital twins and the door to the metaverse

A brief summary of some of my interactions at the 59th Design Automation Conference, DAC 2022, held recently in San Francisco.


The 59th Design Automation Conference (DAC) was back in full swing with an in-person event this year in San Francisco. Replete with keynotes, technical workshops, panel discussions, and more, along with associated exhibition floor, there was certainly a sense of relief and excitement (at least the ones I spoke to), about the opportunity to meet face-to-face at a very industry focused event.

As far as common themes at the event, undoubtedly it depends on who you speak to. In my conversations and meetings, there was very much a focus on areas like intelligent system design, cloud-based design, verification, and digital twins, plus a lot more emphasis on pushing RISC-V (more of that later).

My favorite quote, not for any reason apart from helping to understand the relevance of the metaverse, has to be from Ravi Subramaniam, vice-president and GM at Siemens EDA, when he said to me, “The digital twin of the industrial environment is the door to the metaverse. As a result, other digital twins can be the door to the metaverse for other industries.”

Siemens-Nvidia process simulation
(Image: Nvidia)

This was a reference to the recently announced partnership with Nvidia that connects Siemens Xcelerator and Nvidia Omniverse to enable an industrial metaverse with physics-based digital models from Siemens and real-time AI from Nvidia, to help enhance industrial automation. In fact, I had seen this in action at Nvidia in Santa Clara the week before DAC, and I can certainly say the digital twin of the many environments I saw, from the Amazon warehouse to various industrial settings, were indistinguishable from the videos of the real locations.

You can listen to our interview with Subramaniam in this podcast episode of embedded edge with Nitin here.

The DAC 2022 conference keynotes were given by Mark Papermaster of AMD, Anirudh Devgan of Cadence, and Steve Teig of Perceive. Their focus respectively was on advancing EDA through the power of AI and high-performance computing, computational software and the future of intelligent electronic system design, and machine learning for real: why principles, efficiency, and ubiquity matter.

Papermaster set the scene and something we’ve become accustomed to hearing – about the challenges posed by die size limitations, power and performance, transistor efficiency, and cost and productivity. All require design as well as design automation.

He chose to focus on the need for more ecosystem partnerships and collaboration to push beyond the limitations posed by these challenges. In his words, he said, “We must collaborate as an industry, we have to have a shared vision of the problems we have to solve, and we need a common view of the challenges.” He went on to talk about the use of high-performance computing, or HPC, needed to generate next generation devices, and how design technology co-optimization, or DTCO, is the only way we are going to realize the complexity of new process nodes. Chiplets, he noted, will play an increasingly important role in enabling the next generation of devices.

Collaboration and ecosystems were also a key part of Intel Foundry Services’ participation at DAC 2022. In my conversation with Rahul Goyal, vice president of design ecosystem enablement at IFS, he talked about being part of a customer’s innovation pipeline, providing access to EDA tools, IP, PDKs and so on through its ecosystem partners.

Some of the threads of the conversation align with a panel I moderated on ‘democratization of silicon’ at DAC, as well as a meeting I had the previous week in Santa Clara with the founders of Silicon Catalyst. On the democratization of silicon, Goyal talked about working with universities, startups, and making shuttle access more available. And then the whole concept of the ecosystem program is similar to Silicon Catalyst, with the big difference that Silicon Catalyst has aligned with the ecosystem to provide in-kind benefits to startups in its incubator program.

Goyal also talked about RISC-V. He said, “We are ISA agnostic, but RISC-V is nascent, so sometimes needs more help [in promotion]. RISC-V is particularly popular in India and China, and this creates new markets.”


In fact, as you’ll hear in my two podcasts from DAC that there’s a lot more focus on RISC-V. Dave Kelf, CEO of Breker, told me RISC-V is certainly gaining momentum. Kelf highlighted how they’re working with SiFive and some other processor vendors, and the company also joined RISC-V International and announced a partnership with Codasip for robust commercial-level RISC-V verification.

In my podcasts, Sandeep Mehndiratta, VP of cloud at Synopsys, talks about macro trends and learnings around cloud-based EDA. In particular, he said, “Cloud is not a ‘lift and shift’ model. Customers need help in migrating their current flows to cloud.” Frank Schirrmeister, group director for solutions and ecosystems at Cadence, talked about the role of EDA in addressing the hyperconnected world, including sustainability, optimizing carbon emissions in automotive and data centers and everything from a low power perspective.

Mohamed Kassem, co-founder and CTO of Efabless Corporation, emphasized in our chat what democratization of silicon actually means and how you can enable not just skilled engineers but a wider audience to build their own chips.

In the second podcast from DAC 2022, I spoke about post-quantum cryptography, eFPGAs, connectivity IP and chiplets, and more with PQShield, Flex Logix, proteanTecs, Arteris, Menta, and Alphawave.

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