DCD has an ASIC/FPGA IP Core for Smart Card Reader Apps - Embedded.com

DCD has an ASIC/FPGA IP Core for Smart Card Reader Apps

Digital Core Design (DCD)  has just released a soft IP core that will make it easier for embedded developers to build smart card reader SoCs designs based on ACIC or FPGA silicon technology.The DSMART soft IP core is based on ISO 7816-3/EMV4.2 requirements and incorporates everything needed to handle both the T0 character-oriented protocol and the T1 block-oriented protocol.It provides a communication interface with a smart card, based on ISO 7816-3/EMV4.2 requirements. Designed to combine highly reduced CPU utilization and low area consumption, it can activate and deactivate cards, perform resets, handle ATR reception and many additional features. Configuration options include the ability to adjust the DSMART to specific design needs requiring proprietary options most suitable for the design. Data transfer to and from the host system can be interrupt-driven or executed through Direct Memory Access (DMA). The automatic convention detection and decoding mechanism ensure the exact result regardless of the used convention. Elementary Time Unit (ETU) – time duration of the one bit is decoded from the received ATR interface byte and generated automatically. The card clock divider provides non-gated clock with a wide range of possible frequencies. Also implemented in this softcore IP block is a special power down mode by which the card clock can be held in two possible states, depending on the card parameter. The DSMART incorporates also an optional CRC/LRC hardware checking and generation mechanism which gives the convention independent result. The received CRC/LRC is not stored in the FIFO, but can be read in a case of CRC/LRC error. There is also an optional block length counter provides security of the DMA block transfer and automatic CRC/LRC, subjoining with a manual affixing option. The special block mode handles block transfer automatically. Status and error registers provide necessary information about the FIFO state, errors and card events.

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