Celebrating its 14th year as a Intellectual Property provider of integrated cicuit building blocks, Digital Core Design (DCD) has just released an IP core that could be as popular to System on Chip designers as the orginal Inter-IC bus or I2C.
It's the DI2CSB IP Core, a two wire, bidirectional serial bus desgined to provides stable and efficient short distance data transmission between numerous devices and acts as an interface between a passive target device (such as memory, LCD display, pressure sensors etc.) and an I2C bus.
The DI2CSB core incorporates all features required by the I2C specification and supports Standard, Fast, Fast Plus and High Speed transmission modes.
A very simple interface, composed with read, write and data signals, allows easy connection to target device, it is a technology independent design that can be implemented in a variety of both ASIC and FPGA technologies.
According to DCD's Piotr Kandora, it can work as a slave receiver or as a transmitter depending on the working mode determined by the master device.
He said the core does not require any programming and is ready to work after power up/reset. The read, write, burst read, burst write and repeated start transmissions are automatically recognized by the core.
Based on a static synchronous design, the fully synthesizable block supports several transmission speeds: sandard (up to 100 kb/s), fast (up to 400 kb/s), Fast Plus (up to 1 Mb/s), and high Speed (up to 3,4 Mb/s). It can be operated from a wide range of input clock frequencies.