Digital Core Design has introduced the DHDLC soft IP core, designed to control HDLC/SDLC transmission frame and optimized for great variety of 8-, 16- and 32-bit MCUs. The DHDLC is a technology independent design, therefore can be implemented in both ASIC and FPGA.
The DHDLC IP core saves MCU time wasted n handling HDLC/SDLC features, like bit stuffing, address recognition and CRC computation. To enable even more productivity, the DHDLC has an implemented FIFO buffer, for both receiver and transmitter.
The DHDLC IP Core is fully synchronous with one clock domain design. All parameters are configurable by CPU, and all the parameters can be set by modification constants in a source file.
- Two separate receiver and transmitter interfaces.
- Two separate, configurable FIFO buffers for receiver and transmitter
- Bit stuffing and unstuffing
- Address recognition for receiver and address insertion for transmitter
- Two or one byte address field
- RC-16 and CRC-32 computation and checking
- Collision detect
- Byte alignment error detection
- Programmable number of bits for idle detection
- NRZI coding support