Tektronix Inc.,has developed a complete DDR2 protocol debug and validation solution for the TLA6000 logic analyzers which provides everything needed to validate and debug the operation of memory sub-systems in designs.
DDR2 memory systems are commonly implemented as a bus on the microprocessor or as a block in an FPGA. The complexity of the DDR2 protocol and the number of command/data/address signals make it difficult to both visualize the operation of the bus and to isolate any potential problems. It is also important to ensure that signal timing and interfaces comply with JEDEC standards.
Tektronix says users will not need to be a DDR2 expert to get expert-level results as the included software translates the raw captured data into meaningful DDR2 bus transaction views, and finds and reports protocol violations automatically.
The options for the TLA6000 Series consists of a set of tools designed to provide visibility to all address, data, and control signals. The bundle includes memory chip interposers that provide a convenient way of probing embedded DDR memory systems and eliminates the need to design in probe access points. These memory chip interposers work with the iCapture Analog Mux feature of the TLA6000 to provide a single probing solution for both the logic analyzer and oscilloscope, saving time and minimizing setup complexity.
Protocol decode software is also included and shows all of the DDR2 transactions as well as providing triggering on DDR2 events. Sample point analysis software t automates the process of correctly configuring the TLA6000 Series to accurately sample the DDR2 signals. Protocol violation software finds and reports any violation of the JEDEC-defined DDR2 protocol.