The power struggle between DDR2 and DDR3 continues the tradeoff game between bandwidth and latency. The timing shifts required by the DDR3 flyby topology change the time at which byte lanes demand power by utilizing additional Delay Lock Loop within the controller itself. More DLL's require more power and generate heat as a byproduct.
As the shifts in timing for read and writes are spread out, the demand for power over time dramatically reduces the impact on instantaneous demand on SSO. This is a definite advantage for the memory module where memory reads are generated. DDR3 also introduces a lower voltage further reducing power consumption.
The demand for low power in embedded applications has finally been echoed in the voices at the standards organizations. As the voltage levels for memory devices are reduced, the difference in absolute value between the core voltages and interconnect voltages has become smaller and smaller.
Since power consumption relates directly to core voltage, the reduction in power consumption from generation to generation of DRAM memory is rapidly diminishing.
The problem grows as we look into the arena of stacking components or stacking die into packages where thermal dissipation plays a predominant role; next generation generally means larger die size and more transistors consuming more power and generating more heat.
Questions Of Balance
The big question is NOT how low can the voltage go to reduce power consumption. The question has become what can be done at the channel level to impact power consumption now that interconnect functions are at approximately the same order of magnitude that core voltage reductions will make.
Beyond this, how do engineers balance the needs of the standards organizations driven by the PC market to the needs of the embedded market segment?
The problem itself stems from reference designs that are focused to support PC specific applications while embedded system designers are limited to a selection of processors and memories from this arena.
Get Creative To Reduce Power
How to reduce power demands and ultimately thermal output is currently a very popular and priority issue. There are a number of solutions being provided by various controller companies, for example a low power system that works for a single memory module where the controller has a higher impedance driver (lower power driver).
The memory channel then utilizes higher termination impedance, further reducing the power consumption. This can be used in conjunction with the lower power (lower voltage) DDR memory parts that are just starting to come out from the memory companies ( i.e. DDR2 using 1.5 V instead of 1.8V). These solutions are limited in availability and do not take advantage of the mainstream so they end up being much more costly.
A study of available driver strengths, series dampening resistor values and termination techniques varying ODT settings has shown some promising results. Since the DQ bus is essentially the source of power consumption for the memory parts we looked closely at the several options.
Most of the memory companies have reduced drive strength capabilities for their parts. Reduce drive strength part studies indicate that the part is current and voltage limited which is really a good thing since it keeps the slew rates up there and has only the limitation of how much load it can drive into before timing push-out from the impact of the RC time constant reduces the slew rate too far.
This pretty much limits the lower drive strengths to no more than a 2R system which essentially is the sweet spot for memory in embedded systems these days.
Termination can now be looked at in a simpler manner than before because we have left the confines of the PC developer world and are able to make changes to termination to further reduce power consumption. Increasing the value of ODT termination impacts the circuit jitter and slew rate. The jitter increases as pull-up termination strength decreases.
The slew rate however improves as the pull-up termination increases and we gain back some of what we have lost. A similar effect is found when reducing the series resistor values from the 22 ohm industry standard to a 3 ohm value. In fact the impact on the slew rate is dramatic when coupling the reduced strength memory driver with the lower value series resistor.
Low power DRAM most certainly has its appeal to add its own contribution to improve on the low power problem. This is accomplished by lowering the operational voltages for the memory channel itself. All of the techniques listed above will continue to benefit when reduced voltage parts are used instead of standard parts.
Think Big For Small Space Design
These issues are clearly being recognized as DDR3 has reduced the DQ series terminating resistor on the module to 15 ohms and it is highly likely that DDR4 will require further significant changes of this nature as it becomes solidified. ODT termination capabilities for programming specific memory modules and the controller's capability to be programmed to support user defined ODT settings for reads and writes is also a definite limitation.
Some controllers will allow the user to generate their own ODT settings and some will not. It has become increasingly evident that schemes like read and write leveling for optimizing DDR3 controllers will indeed span the scope of ODT optimization and fall in line with improved performance at reduced power.
Not every company using embedded memory applications does extensive simulation work. The main reason for this is working within the framework of a specific reference platform from the controller company generally insures getting in the ballpark.
By contrast, working in the area of characterizing where specific termination applications improve the channel performance and/or reduce the power consumption provides the means to have a better product.
Additionally this insures a solution that works to controller company specifications. Top level involvement with standards organizations insures that there is a standard behind the part chosen, confirming availability of that all important second source.
Thinking out of the box in the embedded world has its caveats. Primarily the difference between the PC world and the embedded arena is that most embedded applications do not have the customer replacing memory modules within the system. This allows for moving to a memory module with non-standard termination values.
Within the standards organizations themselves, industry sponsors are capable of introducing new designs that become standards through this process. The controller and memory part suppliers also see an emerging need for these lower power applications and have become far more supportive of this kind of parallel standard.
Bob Cox is Director of Engineering at Virtium Technology