Dealing with clock jitter in embedded DDR2/DDR3 DRAM designs: Part 3 -

Dealing with clock jitter in embedded DDR2/DDR3 DRAM designs: Part 3

As previously discussed in Part 1 andPart 2 in this series, measuredDDR2/DDR3 clock jitter values are not absolute, but the specificationlimits are. This presents a problem: is the measured clock jitter apassing value if it is not violating the absolute specification limit?This is unlikely since clock jitter is a random event and it is notpossible to measure the worst-case clock jitter event. So, whether ameasured value is passing or failing depends on several factors.

Recall that if the clock jitter specifications are violated, theclock jitter's adverse effect on the input timings can be neutralizedby increasing the clock period. This suggests that the clock jittervalue itself is not the issue; the issue is how much the input timingis adversely affected by the clock jitter.

Also as previously mentioned, until a statistically sound standarddeviation (sigma, s) value for the clock jitter is obtained, the clockjitter investigation is incomplete. A statistically sound standarddeviation value depends on two factors: (1) the sample size used tomeasure the clock jitter; and (2) the system BER target.

When investigating clock jitter statistically, only the negativeclock jitter only needs to be looked at. For device functionalityconcerns, the DRAM is adversely affected by negative clock jitterviolations, not positive clock jitter violations.

And when the output timings are evaluated, the positive clock jitterresults should mirror the negative clock jitter results. Additionally,since the clock jitter is Gaussian, all the clock jitter values shouldtrack each other. Analyzing t JITper and how it iscompensated for generally ensures that the other clock jitterspecifications will not be an issue.

Clock Jitter Sample Size andStandard Deviation
From past experience, most if not all clock jitter samples areevaluated without any regard for sigma. After inquiring, it wasgenerally found that the clock jitter values were acquired with enoughsamples to yield a clock jitter value that was about 3 or 4 sigmas. Forexample, if t JITper MIN was measured to be “120ps, then asigma in the range of 4 would not be unexpected.

This would mean that sigma is about 30ps. Experience has shown thatuntil enough clock jitter samples are acquired to obtain a t JITperMIN value that is 6 sigma away from the nominal clock, or tCK(avg), notenough samples have been acquired to obtain a reasonably stable sigma.

Using the previous 3ns DDR2 SDRAM (DDR2-667) example with themeasured t JITper(MIN) of “120ps and 30ps sigma, it wouldappear the t JITper(MIN) limit of “125ps is not violated andthe system is good to go. Even then, considering that clock jitter israndom and results in a Gaussian distribution, a 4-sigma clock jittermeans almost all of the clock periods are within specification. Lessthan 0.1% of the clock pulse widths will be lower than specificationsallow, as shown in Figure 6 below.

Figure6: 4 Sigma t JITper Example

BER Targets
Although the previous clock jitter analysis examples seem to provide apositive outcome; further study actually reveals the measured clockjitter is predicting a noticeable potential for failure. The reason itis a “potential failure rate” is because the clock jitter analysis isonly identifying clock timing errors and not all clock errors result ina DDR2/DDR3 functional failure.

The analysis does not go far enough because it didn't determine whatthe system BER target is and how well the clock jitter would respond toit. Applying DDR2-667 to clock jitter with t JITper(MIN) of”120ps and a sigma of 30ps, approximately one clock out of every 31,574clocks will have one clock period less than the minimum allowed atDDR2-667, as shown in Table 3 below. Thismeans the clock period will be too small once every 94,700ns, or 94.7microseconds.

Table3: Standard Normal Distribution Probabilities: BER at DDR2-667, 4 Sigma

If the initial clock jitter analysis stopped with the measured t JITper(MIN)of “120ps and ignored the sigma, it would be the same as saying thesystem is allowed to have a BER of 4 sigma, resulting in a minimumclock period violation once every 94.7 microseconds.

The system BER for clock period violations due to clock jitter mustbe defined before a thorough clock jitter analysis can be completed.DDR2/DDR3 have a defined SER, which means the DRAM will fail once inawhile. Since the DDR2/DDR3 SER rate is so low, the defacto BER for SERevents is extremely high and is ignored.

Clock timing has also had a high defacto BER for clock jitterrelated violations; however, as clock speeds have increased, clockjitter has become a large enough percentage of the clock period that itshould no longer be ignored.

All memory systems do not require the same BER for clock jitter, butsurely something more than 4 sigma is required. Six sigma is often usedas a good quality target.

With the t JITper(MIN) 6 sigma measurement equal to the t JITper(MIN)specification limit, a probability of one clock period violation due tot JITper(MIN) will occur once every 3.04s, as seen in Table 4 below. Such a low BER isunlikely to satisfy most memory application needs.

Table4: Standard Normal Distribution Probabilities: BER at DDR2-667, 6 Sigma

BER targets need to be much higher. BER targets in the range of 10to 11 sigma should satisfy most memory application needs. (Table 5 below. ) A BER target of 10sigma translates to a t JITper sigma of 9″12ps for DDR2 and7″10ps for DDR3.

Table5: BER at DDR2-667 with 10,11 Sigma Targets

Take the previous example of t JITper(MIN) of “120ps witha sigma of 30ps. A BER of 4 sigma or 6 sigma is not acceptable foralmost any memory system. A BER of 10 sigma may be acceptable since theclock violation is only once every four months of continuous clocking.

At 10 sigma, the clock period can be expected to be violated by175ps (10 * 30ps – 125ps). So, instead of the initial clock jitteranalysis suggesting the clock jitter was within specifications, itshould show that the clock period t CKavg should beincreased 175ps to ensure a satisfactory BER for clock jitter effectand acceptable DDR2/DDR3 functionality.

DDR2/DDR3 clock jitter is commonly misunderstood. It is extremelyimportant to analyze clock jitter both when the DLL is locking and whenit is locked. When the DLL is locking, the cycle-to-cycle clock jittermust be kept very low. Once the DLL is locked, the DRAM is fairlyinsensitive to cycle-to-cycle clock jitter, but the clock period jitterand half-period clock jitter need to be analyzed.

It is extremely important to obtain the clock period clock jitter'ssigma when measuring clock jitter. Without knowing the sigma, it isimpossible to know if the measured jitter value is acceptable.

Once the clock jitter is measured and a statistically sound standarddeviation is obtained, clock jitter violations can be neutralized; thatis, the clock jitter may violate specifications but it can still beallowed if the timings are adjusted to account for the additionalerror.

To read Part 1, go to “Defining Clock Jitter .
To read Part 2, go to “DDR2/DDR3 Functionality.”

Scott Schaefer is a SeniorApplications Engineer for MicronTechnology's DRAM group. Mr. Schaefer joined Micron in 1989 and hasspent his Micron career focused on the field of DRAM applications.Prior to Micron, he worked for Synertek and IMP. Mr. Schaefer has over25 years of experience in the electronics industry and has over 50DRAM-related patents.

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