Dealing with multi-Vt & multi-voltage domain timing/temperature inversion challenges

Scaling down CMOS technologies to 40 nm and below is imposing new challenges for physical design engineers relating to timing closure in their designs. In higher technology (90 nm and above), process, voltage and temperature (PVT) corners with the highest temperatures used to be the worst locations for synthesis.


Definition of Terms

Whereas at 90 nm and above, the delay times of a cell increases as temperature increases (Figure 1 below ). But as we move to lower technology nodes (65 nm and below), it is necessary for designers to pick the libraries corresponding to the lowest temperature PVT because of temperature inversion effects where the delay of the cell actually decreases with increase in temperature.

Figure 1. Delay Variation with temperature
To confirm this effect in our designs using 40nm technology, we did few experiments. In this paper we will discuss those results and a few other factors associated with the temperature inversion effect. Analysis was done at cell level on a single inverter and the above behavior was confirmed (i.e. higher delay at lower temperature) as shown in Figure 2 below , with a Standard VT (SVT) library and core voltage of 1.1V.

Figure 2. Delay Characteristics of single stage inverter (To view larger image, click here)
In the above analysis, delay of the cell was measured at different temperature values. But the transition on the input and load at the output of inverter they often are assumed to be the same. So, the above analysis is not accurate as in reality, both input transition and input load are bound to change with temperature i.e. transition and input load increases with increase in temperature as shown in Figure 3 below.


Figure 3. Variation of input capacitance and input transition with temperature. ( To view larger image click here)
The delay of a cell is direct function of both input transition and output load. As shown in Figure 3, input transition and input capacitance are lesser at lower temperature, so delay of the cell at lower temperature can actually be less as compared to higher temperature when used in real SoC designs because the input capacitance of cells will actually contribute to output load of its driver.

To explain the above reasoning, the simulations needed to be carried out on a chain of inverters connected in series. We used 5 inverters in series as shown in Figure 4 below .

Figure 4. Delay Characteristics of chain of inverter at 1.1V. ( To view larger image, click here)
In this case, the following was observed:

1. A constant value of input transition and output load across temperature is applied at the input and output of the circuit respectively.

2. Delay of the middle (third) inverter is measured by varying the temperature only. The variation in input transition and output load of this third inverter will automatically come into calculations. Here, the trend line completely reversed as compared to that observed in a cell level analysis shown in Figure 4 above .

The results we have shown are not in line with the normal assumptions made about temperature inversion effects. Why this is so may have to do with the fact that the temperature, input transition and output capacitance are not the only factors that govern the delay characteristics of a cell.

The variation in cell delay with temperature depends on the circuit voltage as well. In this case, when the voltage of the circuit is reduced to 0.9V, the trend line (as shown in Figure 5 below ) followed the temperature inversion effect perfectly showing higher delays at cold temperatures.

Figure 5. Delay Characteristics of chain of inverter at 0.90 V( To view larger image, click here ).
Based upon above mentioned experiments, it is fair to conclude that for 0.90V (i.e. for low voltages), the worst setup timing corner is the worst-cold and for 1.1V (i.e. for comparatively higher voltages), worst setup timing corner is the worst-hot.

However things became more exciting and complex when the same analysis was carried out on cells with different Vt values across various voltage levels. We generated Vt variants of library values by changing the doping concentration. These are High-Vt, Std-Vt and Low-Vt. Also the SoC is partitioned in different voltage domains.

To capture the whole picture as in the real design scenarios, analysis was done on all the cell variants at different voltage levels (0.9V, 1.0V and 1.1V)

These results (Figure 6 below ) showed that High-Vt cells shows more pronounced temperature inversion effect at lower voltages (0.9V) but at higher voltages the hot temperature still act as worst corners. Std-Vt cells are similar to High-Vt though the impact in delay due to the temperature inversion is moderate. Low-Vt cells are almost immune to temperature inversion effect from the voltage range of 0.9V to 1.1V.

Figure 6. Delay Characteristics of chain of inverter at 0.90, 1.0V, 1.1V with Vt variation. (To view larger image, click here. )
This ambiguous behavior at different voltages with multi-doping taken into account is caused by a race condition between the mobility and threshold voltage (Vt) effects on the cell to dominate the delay.

From results described elsewhere in the technical journals, it is clear that the cell delay is inversely proportional to the mobility and directly proportional to the threshold voltage (Vt). Also, mobility and threshold voltage (Vt) both decreases with increase in temperature. So, as the temperature increases, the delay of the cell can

* Decrease due to decrease in threshold voltage (Vt).
* Increase due to decrease in the mobility.

Therefore, because the delay of a cell may decrease or increase depending on the dominant effect of mobility and threshold voltage (Vt), that is what defines the resulting thermal trend related to temperature inversion effects.

As seen in the results, at 1.1V (the gate overdrive voltage) is large enough so that the decrease in threshold voltage due to temperature variation is negligible. But the mobility effect dominates, with the result that the delay of the gate increases with temperature increases.

But at 0.9V the gate overdrive voltage (Vdd ? Vt) has reduced such that the decrease in threshold voltage effect dominates and delay decreases with the increases in temperature.

So, at 40nm and below, the threshold voltage (Vt) has not been reduced much but the supply voltages has reduced considerably to cater low leakage power concerns. The result is that the gate overdrive voltage (Vdd – Vt) has reduced and thus more prominent temperature inversion effects are observed.

That is why in our analysis, shown in Figure 4 (1.1V) , the delay trend of the inverter did not follow the temperature inversion as compared to the situation in Figure 5 (0.9V). There the overdrive drive voltage was lower (due to lowering of circuit operating voltage), and as a result, the delay trend of the inverter varied inversely with temperature.

Given complex interactions involved and the, high performance and low leakage power requirements of modern design, the recommendation is to use multi-Vt cells (High-Vt cells for leakage reduction and Low-Vt cells for better timing ) as well as use multiple voltage domains (low performance IPs at lower voltages and vice versa ).

Also during actual working of silicon at any given time, it is likely that the temperature and voltage at cell could be different due to OCV effects. In addition, the results of our analysis (no clear cut worst corner), indicate that physical design engineers face some touch challenges if they want to optimize the design for timing before doing final timing closure sign-off.

Design Specifications and Timing Results:
As shown in Figure 7 below the impact of the of such considerations on timing results in a design is that it is no longer possible to close the timing at a single worst corner and live life happily ever after. If not taken into account when scaling geometries while from one node to a lower one could create a mess, if not diagnosed beforehand properly.

Figure 7. Impact on timing results ( To view larger image, click here ) .
As our results show it will continue to be a tedious and iterative task in complex designs to close the timing because of the need to deal with multi-Vt thresholds and multi-voltage domains, due to more pronounced leakage concerns and requirements for higher frequency and lower at nanometer and lower technology nodes.

So, it is absolutely necessary to come up with better methods to deal with such challenges and do so as quickly as is possible. Based on our investigations some possible avenues of exploration should be considered, including:

1 – Optimization in single corners with additional timing margins (clock uncertainty for setup timing).

2 – Multi-corner optimization starting from synthesis. It can be really useful to clean the timing violations in the design in a single go thus helping in overall cycle time reduction without over-killing the design.

3 – For really good silicon results, the final timing sign-off should be robust. As a timing path can be a mix of multi-Vt cells at different temperature and voltage, the worst case corner sign-off may not be sufficient. Additional setup margins in the form of timing deratings or clock uncertainty values on paths having multi-Vt cells should be used.

Rajiv Mittal (Rajivmittal@gmail.com) worked as Senior Member of Technical Staff in ASIC/Layout Design Team in India. Earlier he worked at Freescale Semiconductor as Staff Design Engineer. With more than 11 years of experience he has worked in a wide range of SoC and ASIC design domains, mainly in physical design activities across a number of process technology domains, ranging from 130nm to 40nm

Abhishek Mahajan (b13294@freescale.com) is a Senior Design Engineer at Freescale Semiconductors, Noida, India. He has four years of experience in various domains such as logical and physical Synthesis, Static Timing Analysis, Place and Route and static low power verification.

Hans Jain (hansjain@freescale.com) is working with Freescale Semiconductor as Senior Design Engineer and has experience of ~6 years. He is working in physical design team at Freescale focusing on STA area, Automation and Flow development. He has been involved in 3rd party memory compilers also.

Gaurav Goyal (gaurav.goyal@freescale.com) is working with Freescale Semiconductor as Senior Design Engineer and has experience of more than 3 years. He is working in physical design team at Freescale with Synthesis as area of specialization. He has been involved in several block-level and chip-level designs in technology ranging from 90nm to 40nm. Also, he has been involved in digital circuit designing for the Standard cells in several technology nodes ( 180nm, 90nm, 65nm, 55nm, 40nm ) for a wide range of processes like Bulk technology, Floating gate & Non-Volatile Memory.

This article provided courtesy of Embedded.com and EmbeddedSystems Design Magazine. Sign up for subscriptionsand newsletters. Copyright © 2011 UBM–All rights reserved.

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