# Dealing with PLL clock jitter in advanced processor designs: Part 1

With the advance of faster processors that require faster lines of communication, understanding and characterizing clock jitter has become more important.

Jitter occurs in many different parts of digital applications. Jitter of data with respect to clock in synchronous protocols is one example; jitter of the signal itself in CDR (clock data recovery) applications is another.

While there are infinitely many types of jitter and several ways of measuring it, the choices available and the alternatives that the designer must consider can be narrowed significantly by defining his or her domain a bit more precisely:

**1)** Modern high-speed processors care about how short a clock pulse may become due to jitter before it violates the processor’s guard-banded frequency spec. (Note that the processor’s PLL usually has a jitter frequency transfer function which needs to be taken into account. It is the clock that comes out of the PLL that must abide by the frequency spec). Looking at the definitions of the jitter measurements, it is clear that the processor is concerned about the period jitter.

**2)** When characterizing the jitter frequency transfer function of the processor’s PLL, processor manufacturers often use the lab setup described above (i.e., they really measure TIE jitter).

**3)** Clock driver and oscillator manufacturers do not artificially generate, but rather measure jitter and usually specify it as cycle-to-cycle.

The hardware design engineer, who is faced with three seemingly incompatible definitions, throws in a towel, goes back to school, gets an MBA and joins the marketing department instead. Or (and this happens at least as often), the engineer simply designs the board without checking the jitter specs and hopes that it works.

The purpose of this article is to make such issues less complex and to remove this uncertainty by examining the jitter issues of the clock from which PLL-based processors derive timing as well as analyze the given clock's jitter with respect to an ideal clock, to the degree that the processor’s tolerance requires.

While the issues relating to jitter are examined using a specific processor, the ADSP-TS201S TigerSHARC, much of the discussion also applies to jitter in general and to many PLL-based processor designs.

Unfortunately, unlike more traditional data sheet parameters like setup and hold, analyzing acceptable system jitter is not as simple as merely ensuring that specification numbers are met. There are many ways to measure jitter. On top of that, there are infinitely many different kinds of jitter and the system may behave differently depending on the jitter type.

Thus, before doing any analysis whatsoever, it is important to carefully delineate all of the jitter terms and definitions, first intuitively what they mean, and then the correct mathematical definition.

**Terminology**

An ideal clock that is being jittered is one in which the clock’s edges experience movement with respect to ideal locations.

The jitter of a particular waveform can be measured/characterized as *period, cycle-to-cycle, or time interval error (TIE)* .

*Period jitter. * This measures the maximum deviation of each single period of the jittered clock from that of the ideal clock. In **Figure 1 below** , if

*Cycle-to-cycle jitter. * This measures the maximum deviation of each single period of the jittered clock from the previous period of the same clock. In **Figure 1** , then,

*Time interval jitter. * This measures the maximum deviation of the edge. Figure 1, below, shows this relating to the rising edge; it can also relate to the falling edge) of the jittered clock from the corresponding edge of the ideal clock. In **Figure 1** , then,

Figure 1. Jitter definitions |

Here we presume that at time *t=0* of the measurement, the edge of the jittered clock aligns with the edge of the ideal clock. Note that this is not just a simple aberration of the edge of the jittered clock from the nearest edge of the ideal clock, because the edge of the jittered clock may have “wandered” away from the edge of the ideal clock by more than a full cycle period.

It is time to put clock and jitter under a more precise mathematical definition. We define the* ideal clock of period T and constant amplitude A* as the following function of time *t: *

(usually seconds) and A is measured in volts. Amplitude of the ideal clock is irrelevant to the discussion about jitter, so in all that follows we presume that the clocks have unit amplitude and we consider them as parameterized by T, (i.e., their period):

We also define C_{J,T} (t), the *clock of period T with jitter J(t)* , as the ideal clock delayed by a function of time J(t) (delay can be positive or negative), mathematically:

There are several intuitive reasons for defining jitter this way. The most compelling reason is that jitter is usually generated in a laboratory by applying a function generator signal to a delay input of a pulse generator. This is the way processor manufacturers test susceptibility to jitter. For simplicity we define

These points are precisely where the clock changes from low to high or high to low (thus “r” for *rising* and “f” for *falling* edges). Since what G does outside of these discrete points is completely immaterial, we can presume that G (and, thus J) are infinitely differentiable at all points.

Since these definitions are mathematical in nature and we must maintain real-life plausibility, it is safe to assume that G must be a uniformly increasing function; that is,

since G cannot change the order of the edges, only their locations. Going back to **Figure 1** , we see that

Thus, these definitions naturally lend themselves to specifying jitter as TIE (simply because the maximum amplitude of J(t) is the TIE jitter, as defined in equation (3)). Unfortunately, clock driver manufacturers do not typically specify jitter as TIE. Thus, it becomes important to relate different types of jitter with mathematical formulas.

**Examples of jitter in a DSP/RISC design**

Let’s take a pause from this mild mathematical onslaught and examine different examples of jitter as consequences of our definitions.

**Example 1**

**Example 2**

Intuitively, function J(t) is slowly increasing (or decreasing, depending on the sign of epsilon), and the edges shift uniformly. Note that infinite TIE jitter implies that this jitter cannot be generated by laboratory setup described above; it would require the function generator to output a signal of infinite amplitude. For the same reason, this type of jitter does not occur in real-life systems, so we will restrict our attention to jitter of finite amplitude.

**Example 3**

This type of jitter is appropriately called the *sinusoidal jitter of frequency f _{0} .* In this case, TIE jitter (which, as noted before, is the maximum amplitude of J) is A. Deriving period and cycle-to-cycle jitter is not as trivial as in Example 1, and derivation of period jitter will be done in a following section.

**Example 4**

another ideal clock of period T_{0} and amplitude *A* . It is easy to see that J(t) delays the original clock by A or does not delay it at all. Thus, provided that T_{0} is reasonably smaller than T,

Period Jitter = *A* Cycle-to-Cycle Jitter = *A* TIE Jitter = *A*

**Example 5**

J(t) = White Gaussian noise. The implications of this jitter type on period, cycle-to-cycle, and TIE jitter are postponed to a later section of this series of articles, when we discuss general case jitter.

* In Part 2 of this series the authors will cover “ Dealing with jitter frequency domain transfer functions through a PLL” . The topic of Part 3 will be “Guidelines for measuring TIE jitter .” *

*Boris Lerner is senior DSP applications engineer and Aaron Lowenberger is a product engineer working on DSPs at Analog Devices Inc.*

For PDF version of Part 1 in **“Dealing with PLL clock jitter in advanced processor designs”** go to Pinning down clock jitter terminology and definitions.