 Dealing with PLL clock jitter in advanced processor designs: Part 2 - Embedded.com

# Dealing with PLL clock jitter in advanced processor designs: Part 2

Without a detailed discussion of PLLs (which, in itself, has little to do with the subject at hand), we can just state that a PLL, being a phase locked loop, is linear in phase and, thus, is linear in jitter.

Although this statement is not as simple as it looks, it is correct and we’ll leave it at that. This is good news, because linear systems can be analyzed in terms of their frequency domain transfer function (i.e., frequency response).

Note that this transfer function is linear in jitter only. A PLL itself is certainly not linear as output with respect to input. Thus, the linear system discussion that follows looks at the transfer of jitter through the PLL only.

Generally, a PLL will have a fairly flat unity gain response up to a certain frequency (because a low-frequency jitter appears as a slowly varying phase that the PLL has enough time to adjust for).

Also, as is the case with all real-life systems, frequency response rolls off at the high end. The locations of these cut-off points and the response between these cut-off points vary among PLLs.

The jitter transfer function for ADSP-TS201S processors with a base clock of 125 MHz and PLL multiplier set to 4 is shown in Figure 2, below .  Figure 2. Jitter Transfer Function

Another important factor in this analysis is: given a clock at the processor maximum allowed frequency, by how much can a clock period shrink before failure? In case of ADSP-TS201S TigerSHARC processors, this value is 40 ps (i.e., 2% of the 2 ns period of a 500 MHz clock).

Armed with this data, it is time to analyze jitter tolerance. We begin with sinusoidal jitter.

Sinusoidal Jitter
The sinusoidal jitter of amplitude A (measured in time units, say seconds) and frequency From the previous discussion, we know that A is the TIE jitter.

This jitter inputs into the PLL of the ADSP-TS201S and outputs   We now invoke the Intermediate Value Theorem from beginner calculus, which states that, given a continuously differentiable function, the difference of this function’s values at the end points of an interval equals the length of that interval times the derivative of the function at some point inside the interval. We thus obtain: We now use Figure 2 to find the worst (i.e., maximal) value of . Note that the curve in this figure rolls off at the high end at the rate of 12 dB/oct.

This means that every time we double the frequency, amplitude is divided by 4. Thus, is maximized at the beginning of the roll-off curve (i.e., at approximately 7 MHz) where the PLL actually boosts the jitter amplitude by about 5 dB. Thus,  The ideal clock input in this case is 500 MHz (125 MHz input multiplied by PLL by a factor of 4 ( see Figure 2 ), so Thus, in the case of sinusoidal jitter, to satisfy the 40 ps of period jitter required by ADSP-TS201S processors, we must ensure that the TIE of that jitter is no more than 253 ps. Unfortunately, one usually cannot assume that the jitter will be sinusoidal in nature, in which case the above analysis does not apply completely. But it does show how estimating the absolute value of the derivative of the jitter relates TIE to period jitter. Note that the above analysis can be performed more simply, without referring to the derivative.

The reason that we did it in the more complicated way is because most of this argument will apply when we analyze general case jitter. We will now turn our attention to this more difficult case in the next part in this series of articles.

For Part 1 of this series go to “ Pinning down clock jitter terminology and definitions.” The topic of Part 3 will be “Guidelines for measuring TIE jitter .”

Boris Lerner is senior DSP applications engineer and Aaron Lowenberger is a product engineer working on DSPs at Analog Devices Inc.

For PDF version of Part 2 in “Dealing with PLL clock jitter in advanced processor designs” go to “Jitter Frequency Domain Transfer Function Through a PLL”.

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