Dealing with PLL clock jitter in advanced processor designs: Part 3 -

Dealing with PLL clock jitter in advanced processor designs: Part 3

Before we discuss the guidelines that the developer must follow when measuring TIE jitter, it is useful to also look at jitter for a much more general case in which jitter is not assumed to be sinusoidal.

Here we will look at a general case of input frequency, output frequency, PE tested guard band, peak of the transfer function and the tradeoffs of running the processor at higher speed in exchange for a tighter jitter spec. We will need some more definitions:

As shown in the analysis outlined earlier in this series, it is very important to try to estimate the absolute value of the derivative of the jitter function on the output of the PLL.

is the output of a filter whose impulse response is h’ and input J. Since,

This is actually not completely true. For example, a unity gain filter can increase instantaneous amplitude of its input, overshoot of a low-passed step input is a common example.

But this is very close to being true because the phase response of a PLL’s jitter transfer function is usually fairly well behaved, so instantaneous gain is close to overall gain of the filter and, thus, the inequality above is close enough.). Now,

Converting the definition of TIE jitter
Now that we know that the TIE jitter measurement is ultimately what we want, some guidelines are necessary to convert the definition of TIE jitter as given by the equation (3) from Part 1 in this series into a measurement that makes sense in the real world that we live in. The problem, of course, is that the definition in (3) is theoretical in nature; the maximum is taken over an infinite number of indexes, in other words, over an infinitely long period of time.

This would be rather difficult to reproduce in laboratory conditions. A greater length of time is needed to analyze a lower frequency content of jitter and, as shown by the equation (9), our TIE jitter tolerance is inversely proportional to the jitter’s frequency.

So, let us analyze the example at hand. Our clock frequency is 125 MHz (i.e., each cycle is 8 ns long). It is highly unlikely that this clock has more than 100 ns of TIE jitter (it would have to jitter by more than 12 periods of the clock!), if it does, there is something fundamentally wrong with the board’s design.

We know from the previous section that a 7 MHz jitter frequency allows about 250 ps of TIE jitter. By the inverse proportionality mentioned above, a 17.5 KHz jitter frequency should allow about 100 ns of TIE jitter (it is actually even better than that due to the jitter boost at 7 MHz). Thus, if we presume that the total TIE jitter is limited by 100 ns, all jitter content below 17.5 KHz can be ignored. Frequency of 17.5 KHz corresponds to a period of less than 60 s (i.e., measuring TIE over a period of 60 s should do the trick).

Cycle-to-Cycle Jitter
The previous sections relate TIE and pulse jitter. A few words need to be said in the relevance to cycle-to-cycle jitter.

The problem with cycle-to-cycle jitter is that with it as a given, no matter how small, TIE and pulse jitter can be as large as desired. A simple sinusoidal jitter of very low frequency and large amplitude will change very little from cycle to cycle (since its frequency is low), but the accumulated total change from ideal period can be very large.

Thus, a board designer could not use a clock driver whose jitter is specified as cycle-to-cycle without some additional information about the nature of that jitter. In these cases, if such a driver must be used, it may be necessary to obtain a driver evaluation board and measure the TIE jitter. Then one must be careful not to assume that the jitter will measure the same on another board with a physically different driver chip.

It may be necessary to contact the driver manufacturer to understand board issues that contribute to jitter (such as the power supply noise on the driver), deviation of jitter numbers across the chips, and then guard-band the measured number appropriately to ensure that the final result has no more than 250 ps of TIE jitter.

Thus, having reached this point in the article and having survived bombardment of theoretical and practical calculations, the reader still has not been given a way to select a clock driver for our example processor!

Fully realizing that, simply leaving the issue “as is”, would, most likely, also leave the unfortunate reader more than just a little peeved at the authors, we decided to contact a clock buffer manufacturer to see if they can help us resolve this dilemma. We sent the above portion of this article to the applications folks at IDT, who were more than helpful.

They agreed that the cycle-to-cycle jitter specification cannot be used in processor clock designs and were happy to characterize their recommended parts jitter as TIE. For our processor example, they recommended their IDT5T9070 driver. It turns out that the jitter that this part produces depends almost entirely on the quality of its power supply.

The TIE jitter on their clean evaluation board’s output measured 52 ps. At this point they were actually limited by the quality of the input clock that measured TIE jitter of 50 ps. Following this, they modulated the power supply with a 400 mV peak-to-peak wave and bypass capacitors removed (to ensure that the supply is truly modulated this much). The TIE jitter depended on the modulation frequency as shown in Table 1. Keep in mind that the frequency in Table 1, below. corresponds to the power supply modulation frequency. The resulting jitter frequency may be quite different.

Table 1. TIE Jitter of IDT5T9070 with Power Supply Modulated by 400mV Wave.

Note that 315 ps of jitter at 1 MHz will violate the processor’s minimum spec derived above if the jitter frequency is around 7 MHz — this is unlikely to be caused by a 1 MHz modulation of the power supply. Thus, even in the worst case of the supply modulated by 400 mV and all of the decoupling removed, the jitter spec is still met, except possibly, if the supply modulation is at 1 MHz (and even then, it is, most likely, met!).

For Part 1 of this series go to “Pinning down clock jitter terminology and definitions.”
For Part 2 of this series go to “Jitter Frequency Domain Transfer Function Through a PLL.”

Boris Lerner is senior DSP applications engineer and Aaron Lowenberger is a product engineer working on DSPs at Analog Devices Inc.

For a PDF version of Part 3 in “Dealing with PLL clock jitter in advanced processor designs” go to ”Guidelines for Measuring TIE Jitter”.

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