Debugging with Cortex-M3 Microcontrollers - Embedded.com

Debugging with Cortex-M3 Microcontrollers

Before the introduction of on-chip debugging, most software developerswere using expensive In-Circuit Emulators (ICE) forapplication testingon microcontrollers.High-end emulators were connected via complexadapters, and offeredalso extensive instruction and data trace capabilities with complextriggers.

These emulators were based on special bond-out devices thatwere different from the standard production devices and therefore veryexpensive compared to the actual MCU device.

Modern microcontrollers run at high clock rates and come in tiny,high-pin count packages making traditional ICE technology impossible toadapt. Today's microcontrollers offer on-chip debug logic that givescontrolled access to memory, CPU registers, and program execution.

This on-chip debug logic is part of every production device and, toavoid extra chip costs, is limited in complexity. Since it is mostlyaccessed using a standard JTAG interface, the additionalbandwidthrequired for instruction trace is not available.

Most on-chip debug implementations provide only simple run-controldebugging with limited breakpoint features. Cortex-M3 processor-basedmicrocontrollers, however, integrate ARM CoreSight debug technologythat provides useful trace information via a standard JTAG connectorand without the need for costly hardware.

ARM On-Chip Debug Technology
With the introduction of the ARM7TDMI processor ARM provided theon-chip Embedded ICE debug solution. Embedded ICE is a low-costhardware block that provides complete run-control with two hardwarebreak registers that can trigger either on program execution or memoryaccess.

An additional Debug Communication Channel (DCC) allows data exchangewith the user application during program execution. The Embedded ICE isthe standard debug unit for all ARM7 and ARM9 processor-basedmicrocontrollers that are available today from many silicon vendors. Itis widely supported by the tools industry with standard low-cost JTAGinterfaces that eliminate the need for costly hardware adaptations.

Since the Embedded ICE on-chip debug hardware does not provide anydata or instruction trace, some ARM processor-based microcontrollersalso integrate the Embedded TraceMacrocell (ETM).

However the high data bandwidth used by an instruction tracerequires data output lines, in addition to those of the standard JTAGpins. A special ETM emulator connects to these ETM data output linesand interprets the trace information.

In microcontrollers, ETM often shares useful I/O lines that arerequired by the user application and therefore engineers frequentlycannot use the ETM unit. To minimize the I/O pins required fordebugging, the new CoreSight solution provides additional operatingmodes via a standard JTAG connector:

1) A standard JTAG modeusing five I/O pins for the connection to aJTAG chain or legacy JTAG adapters.

2) A Serial Wire (SW) modethat requires only two I/O pins forrun-control debugging. The SW mode is a different mode of the JTAG portthat requires only the pins TCLK and TDI for communication.

3) When working with the SWmode, an additional Serial Wire Viewer(SWV) output on the TDO line can provide data trace, event trace, andinstrumentation trace information.

Table1: Comparison of Debug Features

CoreSight is the debug technology used in Cortex-M3 processor-basedmicrocontrollers. A low-cost JTAG adapter (for example the Keil ULINK2)is all that is required to interface to the CoreSight on-chip debugunit.

In addition to the trace features, the CoreSight unitimplementsadditional break registers and provides on-the-fly memory access duringprogram execution without additional software overhead.

Development Tools
ARM processor-based microcontrollers are widely supported by thedevelopment tool industry. For example the ARM RealView MicrocontrollerDevelopment Kit (Figure 1, below )available from ARM/Keil providesdevice-specific support for more than 260 standard microcontrollers. Itcombines the ARM RealView Compiler with the µVision Debugger/IDEand the RTX RTOS Kernel.

Figure 1: Components of the RealView Microcontroller Development Kit

The µVision Debugger connects to a Cortex-M3 processor-basedmicrocontroller using the ULINK2 USB-JTAG Adapter (Figure 2, below ).ULINK2 allows Flash programming and hardware debugging and supports alloperating modes of the CoreSight on-chip debug unit.

Figure 2: ULINK2 JTAG Adapter connected to Target Hardware

The combination of the MDK and ULINK2 provides the user with acomplete software development environment for Cortex-M3 processor-basedprojects.

The µVision debugger can display memory content and variablesin several familiar formats. Even during program execution the memoryand variables are permanently updated which gives the user an instantview of the current program status. It is possible to set breakpointsthat trigger on specific variable accesses with or without a value, forexample:

BS write my_value /* stop on writeto my_value */

ULINK2 can be configured to use the SWV output pin. In this mode theuser can obtain trace information about:

* Data read and write of selected variables (optionally withtimestamps and PC values) may be reviewed in a Logic Analyzer window.

* Event counters that show CPU cycle statistics which indicaterequired wait states or the idle time of the device.

* Exception and Interrupt execution with timing statistics thathelps optimize interrupt functions.

* Periodic samples of the program counter that identify the locationwhere the program is running in an endless loop.

* User trace data that can output via 32 ITM (Instrumentation TraceMacrocell) registers and may be used for timing analysis or simpleprintf-style debugging.

The SWV mode is non-intrusive and does not require any monitorsoftware or additional CPU wait cycles. To reduce bandwidth for traceinformation, the data capturing can be selectively enabled. The tracedata captured can be reviewed in the µVision Trace Records window(Figure 3 below ) which providesadditional data display filters.

Figure 3: Trace Record window for selective review of all Cortex-M3 trace information.

Logic Analyzer View of VariableTrace
Figure 4 below shows a typicaloutput of the integrated µVisionLogic Analyzer showing value changes of up to four selected variablesover time. This enables changes of any global or static variableincluding struct members to be reviewed. When PC samples are includedin the trace information the button Code Show opens the source codethat creates the variable modification.

Figure 4: Logic Analyze View of variable changes that are provided by data trace records.

Trace Events
The Cortex-M3 processor provides execution statistics that help you todetermine the performance of the hardware and software implementation.The event counter dialog shown in Figure5 below provides in additionto the total execution time information plus the following details:

* extra cycles spent in wait states (when waiting for slow memory).
* overhead introduced by CPU exceptions.
* sleep or idle time of the device.
* load/store units and folded instructions that speed up execution.

Figure 5: The Event Counters dialog provides timing statistics.

ITM Registers
The ITM unit implements 32 stimulus registers that enable additionaltrace data to be output via the SWV output pin. The overhead in theuser application is minor since only a write access to an ITM registeris required.

ITM trace output can optionally include timing information andtherefore this code instrumentation may be used to analyze executiontimes. ITM can be used for any kind of information. In the ITM Viewerwindow ASCII text string transmission is possible via the ITM register0.

Figure 6 below shows asample printf-style debug output whichrequires only the implementation of the following serial outputroutine:

int SendChar (int ch) { /* Writeserial output to ITM */
    while(ITM_Port32(0) == 0);
    ITM_Port8(0) = ch;
    return (ch);
}

Figure 6: Printf-style output using ITM registers

Exception and Interrupt Trace
By enabling Exception Tracing, SWV outputs information about interruptroutine execution in the application. Combined with time stamps,information about number of calls, minimum and maximum execution timeand minimum and maximum time between interrupt calls can also beobtained. A sample output is shown in Figure7 below.

Figure 7: The Exception Trace window shows detailed statistics about interrupt service routines.

Trace Configuration
The SWV trace information can be selectively enabled with aconfiguration dialog. Selective trace output provides the informationrequired to analyze the actual problem and reduces the bandwidthrequired.

The CoreSight technology therefore fulfills the requirements for MCUsoftware development by providing complete debug and trace connectionwith only three I/O pins.

Reinhard Keil is director ofmicrocontroller development tools atARM Ltd. and was CEO and founder of Keil ElektronikGmbH in Munich,Germany, and Keil Software, Inc. in Plano,Texas, which have been sinceacquired by ARM Ltd.

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