Thermal management in microprocessor systems is an essential factor in ensuring an efficient execution of work processes. Teledyne e2v has demonstrated how energy consumption can be reduced by optimizing both the hardware and software level of a processor. In an interview with embedded.com, Thomas Porchez, applications engineer, data processing solutions, highlighted how this technique reduced energy consumption by 46% compared to the value on the datasheet of a specific application.
At the end of a design process engineers often meet energy management challenges, and the small size leaves little room for a heat sink or fans. This can lead to a reduction in performance.
Through an in-depth analysis of the overall system behavior, it is possible to define the best approach to overcome the potential challenges of maintaining a limited power budget and space-saving measures. This can be done by looking at processor CPU load data, core frequency, and junction temperature. Teledyne e2v has been able to offer a method to optimize processors while conserving energy resources and minimizing heat generation.
Static and dynamic power consumption
High processing frequencies impose a strict limit on energy consumption in computer systems as a whole. Therefore, the energy consumption of each device should always be reduced to a minimum. Power calculations determine not only the sizing of the power supply but also maximum operating reliability.
The energy consumption of the processor is typically divided between static and dynamic energy consumption. The static power consumption corresponds to the leakage current flowing through the device and evolves linearly with temperature. The total leakage current of a logic gate includes two major components: subthreshold and gate leakage. The subthreshold leakage current is significant in CMOS digital circuits, it exponentially increases with the reduction of the threshold voltage.
“What is interesting about static energy consumption is that it is not repeatable through paths, i.e. you can select paths to lower energy consumption,” said Porchez.
The dynamic power consumption at the other end is more or less independent of the junction temperature but depends on the CPU load, platform and frequency of the CPU and the peripherals used. This means that dynamic power consumption depends on the application.
The dynamic power consumption is calculated by considering the sum of two factors: switching power and short-circuit power. Switching power is dissipated when charging or discharging internal and net capacitances. Short-circuit power is the power dissipated by an instantaneous short-circuit connection between the supply voltage and the ground at the time the gate switches state.
The Teledyne solution
The practical demonstration was performed with two single-board computers that were designed by Teledyne e2v partners. A T1042 processor with quad-core architecture is placed on each single-board computer and can run up to 1.5 gigahertz.
One processor runs an application that provides 100% CPU loading. The other is a Teledyne-optimized processor that runs the same application and provides 50% CPU loading. An infrared camera analyzes both processes simultaneously. The camera image is displayed on the screen (figure 2).
“Looking at the left processor, we have the temperature of the heat sink is about 71 degrees and on the right that of the right processor is about 59 degrees. So about 12 degrees difference. On the terminals, we see that there is still a huge difference in terms of the junction temperature between the two processes,” said Porchez.
He added, “If we look in detail at the energy consumption process, which is interesting here, we see that the difference between the two processes is between 1.5 and two watts, which is a huge difference.
Teledyne e2v pointed out that this case study can deliver T1042 with 46% power consumption reduction, versus what one would expect by reading the T1042 specification.
“During deep dive discussions with customers, we came to the conclusion that their application was not requiring the maximum capabilities of the processor. Customers were actually worried about the power figures from the datasheet (listed values in high computing scenarios) thus we helped them to narrow down the real power estimation in their case. After this, we were able to translate this in a static power consumption limit, and agreed to deliver parts complying with this requirement,” said Porchez.
Power dissipation is one of the main challenges for integrated circuits. Dynamic power is dominant in CMOS circuits. Dynamic dissipation occurs as a result of switching activity due to short circuits of current and load capacity charge and discharge.
Lower power consumption (in addition to higher bandwidth) will be a dominant factor for the next generation of processors. The global trend towards higher speeds requires new solutions to optimize energy management. One technique that aims at reducing dynamic power consumption involves dynamically adjusting the voltage in a CPU and frequency. This is operation is called dynamic voltage and frequency scaling (DVFS). It benefits from the fact that CPUs have discrete frequency and voltage settings. Porchez highlited that this approach is an opportunity for designers to fit larger processors in applications, where they initially thought it would be impossible due to power constraints. This allows them to get larger computing capability margins in their systems to comply with future use-cases evolutions. He added, “For Teledyne e2v, this is an additional technological differentiator, and at the same time leads to an increased leve of customer intimacy, for which we are already known”.
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