LONDON Tenison Design Automation is demonstrating how its VTOC works with the ARM RealView SoC Designer with MaxSim technology, to incorporate existing RTL into new SystemC ESL designs.
VTOC is designed to support the architectural system modeling process and this software demonstration shows the complete end user experience when using the tools by demonstrating how existing IP can be reused in new ESL design environments at high simulation speeds suitable for design exploration.
Tenison VTOC was developed from research at the University of Cambridge Computer Laboratory and Virata in the mid 1990's. The product was first shipped in 2000 and is now in use by customers around the world including ST Microelectronics, Conexant Systems, Samsung, Renesas and Skyworks Solutions as well as other Fortune 100 companies. While headquartered California Tenison's R&D is still carried out in Cambridge where the demo was developed.
Designed to bridge the 'Model Gap' between the ESL models that have been developed and those that are needed, Tenison’s modeling technology gives designers the ability to move to higher levels of abstraction as well as working in or between different levels. This demonstration shows that many models existing today can quickly be re-used to speed new ESL designs.
Chris Lennard, ESL Strategic Marketing Manager at ARM, said, “The integrated flow from VTOC to RealView SoC Designer helps resolve the issue of legacy RTL IP import to the system-modeling environment.”
Research shows that 80 per cent of a typical new ASIC/ASSP design is reuse of existing design IP written in Verilog or VHDL. Reuse of such legacy IP is key to the adoption of Embedded System Level (ESL) design methodologies and tools. The most effective strategy is to use a tool that can take existing RTL and convert it to models in ESL-friendly languages such as C++ or SystemC for import into ESL tools. This means that in order to take advantage of the full capabilities of a system, IP blocks need to be described in SystemC. Yet, this can be a problem when existing designs or the IP blocks from outside vendors exist only in RTL.
Two demonstrations have been put together, one to show the power of VTOC models of RTL in a RealView SoC Designer environment, the second to show how the technology scales to complete multi-core SoC designs.
In the first demonstration, the features available through use of VTOC with RealView SoC Designer are demonstrated. In this demonstration a specialized compute engine in RTL is converted for use in the RealView SoC Designer. Tenison VTOC Validate is used to demonstrate the model is correct.
The model is then loaded into RealView SoC Designer, and simulated to illustrate the speed and full accuracy of the RTL model—every register has its correct value at every clock cycle; and full debug access to the original RTL hierarchy is available—registers and arrays can be read, written and break pointed from within the RealView SoC Designer tool environment. The second demonstration shows the scalability of this technology to complete SoC designs. The demonstration begins with a complete SoC design captured in the ARM RealView SoC Designer environment. The SoC includes an ARM9 family processor, AMBA AHB bus, and several peripheral pieces of IP. Tenison’s VTOC is used to convert an ARM PrimeCell PL190 interrupt controller from RTL to C++ so that it can be easily included in the design.
Tenison’s Validate is once again used to validate that the SystemC version of the PL190 is the same as the RTL version. The C++ PL190 is then inserted into the RealView SoC Designer environment and simulated to illustrate the full accuracy of the RTL model, while maintaining high performance and offering full debug access to the original RTL hierarchy from within the ESL C++ tool environment.
Tenison has also signed a OEM agreement and technology integration deal to incorporate Spira Tech's Cohesive Transactor Technology with VTOC.