Demystifying phase-locked loops - Embedded.com

Demystifying phase-locked loops

The Phase Locked Loop (PLL) is an indispensible component in modern electronic systems. Its function is to generate an accurate output signal of frequency equal to, or a multiple of, the input signal frequency. It is mainly used in modulators/demodulators and in clock generation and multiplication.

However, when designing a digital communications system on a mixed-signal chip, digital designers tend to avoid PLLs because of their inherent analog nature, and analog designers stay away from them because IDEs involve coding. This article presents a different way of designing a simple PLL. PLL Basics

To begin, let us have a look at the block diagram of a PLL:

Figure 1: Block diagram of a PLL

 

Consider an input sine wave of frequency ?i :sin(?i t) to the PLL. A square wave is an infinite summation of a sine and its harmonics, so although the circuit may be digital, results defined in terms of sines and cosines are equally valid. Let the output of the Voltage Controlled Oscillator (VCO) also be a sine wave of frequency ?0 and phase f:sin(?0 t + f). The input signal enters the PLL at the Phase detector, where its phase is compared to that of the VCO. In simple terms, this phase detector is a multiplier. Recall:

Equation 1

Or if we had started out with cosines instead of sines, we would have

Equation 2

Since cos(A + B) is a high frequency term, it is filtered out by the Low Pass Filter (LPF). Assuming that the PLL is closely following the input frequency, ?i – ?0 ˜ 0 (low frequency signal), this passes through the LPF to generate an output proportional to cos((?i – ?0 )t + f . If ?i = ?0 , the output is proportional to the phase difference f between the VCO output and the input frequency. Thus the phase is detected.

For proper operation, a constant offset that is independent of frequency is added to this voltage by the bias generator, and then the voltage is input to the VCO. As its name suggests, the VCO generates an output voltage whose frequency is proportional to the input voltage:

Equation 3

Where ?0Q is the quiescent or free-running frequency of the VCO (when input=0); KVCO is the sensitivity (rad/s/Volt); VC is the input voltage to the VCO.

Looking at the PLL from a high level, if the input frequency to the PLL is different from the VCO frequency, a voltage is generated by the phase detector. After being filtered and offset, this voltage adjusts the output frequency of the VCO to match the input.

Parameters of a PLL

The key parameters of a PLL include:

  1. Type and order: Determined by the transfer function of the system.
  2. Lock range: The frequency range the PLL is able to follow input frequency variations once locked. Mainly defined by the VCO range and limited by the phase detector.
  3. Capture range: The frequency range the PLL is able to lock-in when starting from an unlocked condition. This range is usually smaller than the lock range and will depend on the LPF cut-off frequency.
  4. Loop bandwidth: Defines the speed of the control loop.
  5. Transient response: Peak overshoot and settling time.
  6. Steady-state errors: Phase or timing error.
  7. Output spectrum purity: Strength of the main frequency versus sidebands.
  8. Phase-noise: Defined by noise energy in a certain frequency band. Dependent on VCO phase-noise, PLL bandwidth.
  9. General parameters: Such as power consumption, supply voltage range, output amplitude.

To read more of this article go to “S-Domain representation.

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