DESIGN AUTOMATION: System-level verification tool rolls - Embedded.com

DESIGN AUTOMATION: System-level verification tool rolls

San Francisco — Cadence Design Systems Inc. is applying the plan-to-closure methodology in its Incisive Enterprise tool suite to the system-level verification of complex system-on-chip (SoC) designs. A new set of enhancements to the Incisive tool is designed to provide an automated end-to-end transaction-based flow from architectural modeling to full system validation. It will help solve the “predictability crisis” around system-level integration, said Steve Glaser, corporate vice president of marketing for Cadence's verification division. “People don't know when they are done, they don't know what to do next and they don't know how to deal with software complexity,” Glaser said.

Glaser estimates that about 30 percent of Cadence's customer base–including most if not all tier-one companies–are wrestling with system-level verification challenges such as the high capacity and scalability required to verify an SoC design that contains a highly complex, heterogeneous mix of logic, memory, intellectual property (IP), embedded software and other components, he said. The solution, according to Glaser, must verify hardware and embedded software together, provide reasonable performance speed and the productivity to ensure that customers can hit time-to-market windows. Customers need the predictability to allow them to establish reasonable product development time lines, Glaser said.

“Sometimes a customer will say, 'maybe a product is not going to be ready for Christmas–maybe it's going to take another six months,' ” Glaser said. “But that might be OK if they knew that from the start and could plan for that.”

Verification has generally been seen as the overall design bottleneck for the past two years, with some saying that as much as 70 percent or more of design time is spent in verification. Problems faced by customers in verification only intensify at the system level, said Ran Avinun, marketing group director for system-level verification. “All of the problems that people are having in verification are being compounded at the system level, often in a very significant way,” Avinun said.

The Cadence answer is a set of enhancements designed to apply Incisive–an established tool that has been successful at block- and chip-level verification–to system-level verification. Executives say the company has combined verification-management capabilities with Cadence's SystemC transaction-based solution spanning SystemC simulation and hardware-based platforms.

Glaser and Avinun said that the enhanced Incisive Enterprise tool–the high-end flavor of Incisive created when Cadence started to segment some of its product lines last year–is the first EDA system-verification solution spanning and linking high-performance engines with an integrated flow, verification management and verification IP. For example, a number of companies offer verification IP, but, the executives said, these models cannot be used in hardware acceleration or emulation.

“This is the first time that any EDA company has attempted to combine high-performance engines with these other capabilities,” Avinun said.

According to Cadence, the enhancements to Incisive Enterprise enable engineers to, among other things, describe and track transaction-level tests and system-level assertions in a master verification plan, control system-level regression tests on high-performance software and hardware engines, analyze failures, rank tests against coverage targets and aggregate total system coverage. The tool also includes a new SimVision debug environment, enhanced to include a common single design hierarchy, source viewer, unified multilanguage assertion browser and waveform debugger–all with multiple abstraction levels and engines for system-level debug and analysis, according to the company. Incisive's plan-to-closure methodology has also been updated to include transaction-based acceleration and transaction-level modeling methodologies to guide design and verification teams through the verification process, according to Cadence.

New system-level capabilities enable the executable verification plan to work directly with Incisive Enterprise Manager, which can now track coverage for directed tests and assertions for software- and hardware-based verification engines based on a common, executable verification plan, according to the company. Cadence is also rolling out new verification IP supported through the Incisive platform, including new brands of assertion- and transaction-based verification IP and new emulation rate adapters, SAS and SATA.

Overall, the enhanced Incisive–the result of what Glaser said was years of development work with some customers–provides five kinds of metrics, as well as five different types of analyses on these metrics, to give customers “insight on what to do next and when they are done,” he said.

Glaser added that all of the money and all of the issues associated with electronic-system-level design, which has been billed as the next logical step and a potential windfall for EDA, are currently concentrated on verification. “Right now, it's all about system-level verification,” he said. “This is an exploding problem.”

The Cadence executives painted the EDA market leader as the company best positioned to provide a system-level verification solution based on Cadence's strong position in SystemC tools and emulation, among other attributes. “None of the other vendors even think about system-level verification,” Avinun said.

The new Incisive transaction-based system-verification solution is available now, Cadence said. The company will be shipping the product this quarter and is currently working with early adopters to implement it, according to Avinun. Pricing information was not disclosed.

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