Design of a low power high speed differential to single ended converter using feedback -

Design of a low power high speed differential to single ended converter using feedback


Editor’s Note: The author describes the design of a low power, high speed differential to single-ended converter circuit that uses a novel feedback technique to achieve high bandwidth without increasing the current consumption.

The differential to single (D2S) ended converter circuit is an important component in many analog and mixed signal circuits such as Phase Locked Loop (PLL). In a PLL, typically the clock phases generated by voltage controlled oscillator (VCO) do not have rail-to-rail swing.

Typically, a D2S converter is employed to achieve rail-to-rail swing at VCO frequency. For multiphase PLLs, such as those used in clock and data recovery (CDR) circuits and in physical links (PHYs), the power consumed by a D2S converter becomes significant because they are employed with each VCO clock phase.

A conventional cross-coupled D2S converter is shown in Figure 1 . INP (positive input) and INN (negative input) are two non-rail-to-rail differential signals. In this circuit, positive feedback ensures rail-to-rail output swing without any leakage current consumption. [1]

However, because of the cross-coupling, there is contention between the pull-up and pull-down transistors because of which it has limited bandwidth and cannot work at high speed (in the range of several MHz). [2]

Figure 1: Conventional cross-coupled D2S converter

Figure 2 shows another widely-used high-speed D2S converter. The bandwidth of this circuit is high because of low impendence at PBIAS node (MP1 is diode connected) [3] and absence of any cross-coupling. However, a significant drawback of this circuit is the leakage current flow through MN1 and MP1 when input INP is HIGH. Effectively, when INP is high, there is a resistance of


between VDD (Voltage drain to drain) and GND (ground).

Figure 2: Conventional high speed D2S converter

A proposed high-speed D2S converter designed to achieve the same goals is shown in Figure 3. This is a modified version of the circuit shown in Figure 2.

Figure 3: Proposed high speed D2S converter

When INP transitions from LOW to HIGH and INN transitions from HIGH to LOW, PBIAS goes low, which turns on MP2 and OUTP goes to VDD. Due to this, MP3 turns off and cuts off the leakage current path through MN1 and MP1.

Initially, since OUTP is low when INP starts transitioning from LOW to HIGH, the proposed high-speed D2S converter is equivalent to the circuit shown in Figure 2 because MP3 is on and PBIAS is close to VDD. To reduce the ON resistance, a large W/L ratio is used for MP3. This helps in quickly charging PBIAS towards VDD when OUTP goes from HIGH to LOW.

Simulation Results
Figure 4 shows the transientsimulation results of the proposed high-speed D2S converter. The circuitin Figure 2 is also designed in the same 28nm CMOS technology, with VDD= 1V for comparison with the proposed high speed D2S converter.

Figure 4: Transient simulation of proposed high speed D2S converter

Figure 5 showsthe transient simulation result. In Figure 4 and Figure 5, a 500MHzdifferential signal swinging between 0 and 0.7V is applied at INP andINN. The single-ended signal swinging between 0 and 1V is obtained atOUTP.

It is clear from Figure 4 that no leakage current flowswhen INP settles to HIGH level. However, as shown in Figure 5, theconventional high-speed D2S converter has a significant amount ofcurrent flowing through it.

Figure 5: Transient simulation of conventional high speed D2S converter shown in Figure 2

Figure 6 shows the DC transfer characteristic of the proposed D2S converter. The trip point is approximately at 0.5V.

Figure 6: DC transfer characteristic of the proposed D2S converter

Simulationresults show that the proposed circuit can work at high frequency andconsumes current only during the input transitions. No leakage currentis drawn from the supply when inputs are static.


1.Khan, Q.A., Wadhwa, S.K., and Misri, K., “A Single Supply Level Shifterfor Multi-Voltage Systems”, 19th International Conference on VLSIDesign, 2006

2. Yu, C.C., Wang, W.P., and Liu, B.D., “A new levelconverter for low-power applications”, IEEE International Symposium onCircuits and Systems, 2001, pp. 113–116

3. Koo, K. H., Seo, J.H.,Ko, M.L., and Kim, J.W., “A new level-up shifter for high speed andwide range interface in ultra deep sub-micron”, IEEE InternationalSymposium on Circuits and Systems, 2005, pp.1063-1065

Sanjay Kumar Wadhwa received his B. Tech. degree in Electronics andCommunication Engineering from the National Institute of Technology(NIT), Kurukshetra, India in 1996. Since then, he has worked in thefield of analog and mixed signal designs for various applications. He ispresently working with Freescale Semiconductor India design centre inthe field of power management and low power analog circuits. He haspublished 15 papers in various VLSI conferences, has four defensivepublications and holds 20 US patents. He has been recognized as aDistinguished Innovator by Freescale Semiconductor. His main interestsare in the design of low voltage, low power, and low area highperformance analog and mixed signals circuits.

Leave a Reply

This site uses Akismet to reduce spam. Learn how your comment data is processed.