Design Teams Set to Embrace Next-Generation Hardware-Assisted Verification Platforms -

Design Teams Set to Embrace Next-Generation Hardware-Assisted Verification Platforms


For engineering teams planning that next leading-edge design project for 2005, the goal remains the same: Better design in less time. A daunting task, indeed, as verification continues to consume 70% of the design cycle. This will only get worse as we move through the year and beyond, and design sizes achievable with sub 0.10 processes push that percentage higher.

Functional verification is the only means of thoroughly debugging a design before silicon availability and the only way an engineering team can meet its goal. And yet, exhaustive functional verification using a software simulator is not a viable solution any longer because of its unsatisfactory performance. Moreover, simulation farms do not address large designs either since they require long sequences of tests that consume billions of cycles and cannot be parallelized.

Hardware emulation is one way to alleviate the functional verification bottleneck because emulators, when properly designed, can execute at megahertz speeds. “Ugh,” you say to yourself as you read “hardware emulation.” And, for good reason should you react this way.

Over the years, hardware emulators have gotten a deservedly bad reputation and are perceived to be expensive technology, complex and hard to use. Recall the industry adage from the 1990s cautioned: “Time to emulation.” That's because traditional hardware emulators were not easy to setup and required months of “tweaking.”

Also, traditional emulation systems built on large arrays of field programmable gate arrays (FPGAs) that amount to hundreds or even thousands perform at sub-megahertz—typically in a range of 100kHz to 300kHz.

All of that is changing as the market begins to embrace new emulation products that use high-end FPGAs. Found to be much easier to use and run at five MHz or more, they are offered at an acceptable price point for engineering teams. These products are priced as low as 1.5 cents per application specific integrated circuit (ASIC) gate, a pricing impossibility for traditional emulators that run in the 10 cents and higher range.

These new products are more hardware-based verification platforms than just another emulation product. That's because they can be used by hardware designers to verify and debug system on chip (SoC) hardware designs, and embedded software developers to validate SoC embedded software.

What's more, you can concurrently debug the hardware and the embedded software. That is, you have two concurrent views of your design, all the internal guts of the SoC hardware and the whole embedded software code. An engineering team can trace and change any of them and monitor the effects. A hardware bug that effects the embedded software code execution can be traced starting from the embedded software and vice versa.

Obviously, these platforms offer a tremendous return on investment (ROI), since the same platform and the same design model can be used for two purposes. Previous generations of emulators were inadequate for validate embedded software, and are too expensive to meet budget constraints of the embedded software community.

Given all this, it's no wonder that a prominent executive from an electronic design automation (EDA) company in the emulation business has compared a four-year old emulator to a bookend. He advised owners of such hardware to throw it over the side of a boat and use it to grow coral. In 2005, no coral will be growing on the hardware-assisted verification platform.

About the Author

Dr. Lauro Rizzatti is vice president of marketing and general manager of EVE-USA. He has more than 30 years of successful experience in EDA and ATE, where he held responsibilities in top management, product marketing, technical marketing, and engineering. He held various positions in companies such as Get2Chip, Synopsys, Mentor Graphics, Teradyne, Alcatel, and Italtel. Dr. Rizzatti has published several articles, viewpoints, and technical papers in the trade press and presented at a multitude of domestic and international technical conferences. He holds a doctorate in Electronic Engineering from the Universita degli Studi di Trieste, Italy.

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