Design Tip: Implementing an SoC with dependable 50% duty cycles -

Design Tip: Implementing an SoC with dependable 50% duty cycles

With the increased integration and movement towards system-on-chip (SoC) designs, it is becoming increasingly challenging to satisfy the diverse clocking requirements of the ever increasing functions and Intellectual Property (IP) circuit blocks. Along with this come diverse clocking needs, ranging from frequency and phase relationships to fulfill jitter specs, sequencing of clock enables, and the lie (layout of the circuit). A multitude of clock frequencies are needed to satisfy the needs of integrated IPs, which has resulted in a complex mix of centralized and distributed frequency dividers and clock controllers. In addition, there are many peripheral and system IPs or functions integrated in a SoC, each with its own internally divided clocks, so it is often difficult to implement an SoC with a duty cycle where 50% clock is required.

This article describes a new approach to implementing clock dividers in a system-on-chip design that supports both high performance and low power. It uses a dual edge counter-based configurable frequency divider that can not only divide the clock frequency for both even and odd configurable division factors, but at the same time maintains a 50% duty cycle of the output divided clock.
Maintaining a 50% duty cycle of the output clock for even division factors is not much of a challenge. But when it comes to odd division factors, extra design efforts are required. So by deployment of a dual edge counter, it is possible to build a configurable frequency divider with a 50% duty cycle of the output clock for both odd and even division factors.

Introduction to clock dividers
A clock divider is a circuit that takes an input signal of a frequency, ƒin, and generates an output signal of a frequency:

where ‘n’ is an integer, i.e. the division factor.

As SoCs get complex due to the integration of more IP-based dedicated function circuit blocks to enhance the functionality of a chip, these blocks often require their own specific clock frequencies, each with its own frequency limitations.

A duty cycle is the time that a circuit block or SoC spends in an active state. In a periodic event, duty cycle is the ratio time it is in an active state versus the time it is in a standby state.

where D is the duty cycle, r is the duration that the function is active, and T is the period of the function. For example, a 60% duty cycle means the signal is high 60% of the time and low 40% of the time.

Conventional frequency divider circuit
Conventional counter-based frequency divider designs make use of binary counters that trigger either on the positive or the negative edge of the clock. The downside in terms of SoC silicon real estate is that this usually requires separate circuitry for odd and even division factors. One such counter-based frequency divider design is shown in Figure 1 .

Figure 1: Conventional counter-based frequency divider circuit

Frequency divider circuit configurable for division factor up to N-1
In our proposed design (Figure 2 ) we use a dual edge counter that gets reset whenever there is a transition on the output divided clock. Not only does this reduce the size of the binary counter, it now only needs to count up to a max value of (N-1) versus (2N-1) in a conventional design. As power consumption is one of the key factors in SOC design, the proposed design uses clock gating to avoid unnecessary dynamic power consumption.

Not only does this approach reduce silicon area – and thus power requirements – it also allows any circuit block in which it is implemented to maintain an output duty cycle of 50%.

Figure 2: Proposed configurable clock frequency divider circuit

The following table summarizes the desired signal value at the output in terms of the division factor N, which may be even or odd.

Table 1: Proposed Frequency Divider Design Approach

The design algorithm we used for the proposed clock frequency divider is shown below in Figure 3 .

Figure 3: Flowchart explaining the steps for the operation of Proposed Design

Figure 4 shows the simulation waveforms for the proposed frequency divider design for both ODD and EVEN Division factors.

Figure 4: Simulation waveforms for Divide by ten and Divide by thirteen

Table 2 shows the results of the use of this new approach in a design that hasbeen figured for a division factor up to 15. It shows that the proposedcircuit has less area and least power consumption when compared againstthe conventional circuit.

Table.2: Comparison of the conventional and proposed circuit

Basedon our analysis and operation in some typical SoC designs, the proposed‘Dual Edge Counter Based Configurable Frequency Divider Design’consistently generates an output divided clock with 50% duty cycle withthe desired division factor. It is also generic in its design approachand implementation and can be used in any complex SoC design to gainmaximum performance and to meet unusual frequency requirements.

Unlikethe fixed factor dedicated approach used in traditional designs, thecounter-based clock frequency divider implementation ensures that thecircuit can be reconfigured for a range of division factors, dependingupon the width of the counter.

Gaurav Goyal works withFreescale Semiconductor as Senior Design Engineer and has more than 3years experience. He is working with the physical design team atFreescale with Synthesis as his area of specialization. He has beeninvolved in several block-level and chip-level designs in technologyranging from 90nm to 40nm. He has been involved in digital circuitdesign for standard cells in several technology nodes (180nm, 90nm,65nm, 55nm, 40nm ) for a wide range of processes like bulk technology,floating gate & non-volatile memory. He can be reached by email at .

Rohit Goyal received his B.E. degree in Electronics and Communication from theNational Institute of Technology, Kurukshetra, India in the year 2011.Heis currently working with Freescale Semiconductor, Noida as a DesignEngineer. His primary responsibilities include FPGA Prototyping,Emulation and Verification. His research interests include high speedand low power design algorithms and architectures.

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