Design tools for 3D ICs remain a challenge - Embedded.com

Design tools for 3D ICs remain a challenge

3D IC tools The 3D IC is now officially the most widely-discussed PowerPoint-only technology in the industry. Save for two known, and important, demonstration projects, at Samsung and Xilinx, the use of through-silicon vias (TSVs) to distribute nets across multiple dice in a stack has so far been confined to research projects and really well-illustrated presentations. As EDN IC Design editor Michael Demler shows in his thoroughly-researched report on the subject this month, this lack of commercial progress has created a chicken'and'egg problem for 3D IC tools.

As Demler points out, there are very substantial challenges to developing a full suite of tools; from floor-planning and system estimation through detailed place, route, DRC, and extraction of nets that include TSVs and interposers. Today the best solutions involve rock-solid 2D tools, chewing gum, and bailing wire, mixed with a great deal of expertise. Therein roosts the chicken, or lies the egg: your choice. The EDA vendors with the ability to integrate a full 3D flow won't move until they see a market, except perhaps to insert some hooks into their open database structures. The start-ups who will move quickly can only do point tools. And until there is an integrated flow there won't be a large market. So once again it will probably fall to TSMC and the Common Platform Alliance to set the schedule on a vital new technology. Please give Michael's report a read and let us know what you think, and where your team stands on the 3D IC question.

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