DESIGN TOOLS: From specs to verification plans, by Relay - Embedded.com

DESIGN TOOLS: From specs to verification plans, by Relay

Santa Cruz, Calif. — As a functional-verification consultant, Steve Burchfiel once had to construct a verification plan from hundreds of pages of continually changing specifications. Convinced that there must be a better way, he co-founded a startup that now claims to have the first tool that generates verification plans from design specifications.

Severity One Inc. (Austin, Texas) is starting to sell Relay, a tool that produces reusable, coverage-driven verification plans from textual specifications or user input through a graphical user interface. It can produce coverage models in the “e” verification language, as well as coverage goals for Cadence Design Systems Inc.'s vManager product.

Burchfiel, the CEO and co-founder of Severity One, is also co-founder and president of Correct Designs, a verification consulting and training company. In 2003, Burchfiel and Correct Designs co-founder Kevin Schott spun out Severity One with the intent of developing and selling the Relay product.

The idea for the product came about when Correct Design was developing a verification plan for a California company that had hundreds of pages of paper specs.

“We did it the good old-fashioned way of pulling out documents and writing a plan,” Burchfiel said. “We saw the enormous need for automation in the planning space.” One driver for this need, Burchfiel said, is large-scale intellectual-property (IP) reuse. “We wanted to find a way to develop reusable verification plans, so when a company sells IP it can say, here's the plan and the test suite and coverage model that matches the plan,” he said.

Severity One hired its own developers, wrote the code for Relay, and worked with two large semiconductor companies last year to prove the technology. Relay is now available for purchase, along with a day-and-a-half training program.

Before its acquisition by Cadence, Verisity developed a verification-planning tool called vManager, which can help users define and track test coverage. Burchfiel said that Relay works at a higher level by generating verification plans from design specifications.

Relay, in fact, can input its plans directly into vManager.

While Relay doesn't require the use of Cadence's Specman or vManager, it does have direct links to those products. Burchfiel said that Severity One is also working on SystemVerilog support.

Relay features a “spec annotator” that has an interface built into Microsoft Word and FrameMaker. As users point to design attributes that need coverage goals, Relay extracts data and calls up a Java-based program to build a verification plan. Burchfiel explained that the plan is synchronized with the Relay database, such that any changes made to the original document will be automatically reflected in the verification plan. Alternatively, if there is no written spec, users can turn to the GUI to tell Relay what checks are needed at the block and system level, and what the coverage goals are. The verification plan can also be modified through the GUI.

The reusable verification plan produced by Relay will have functional-coverage goals, a definition for all stimulus needed and checking requirements for all the checkers. These plans can be fed into vManager to generate vPlans for monitoring coverage. Users can also generate coverage models in “e” that can be directly fed into Specman.

Advantages, said Burchfiel, include faster time-to-market, better verification quality and coverage. He said Relay can provide a threefold to sevenfold productivity improvement in writing verification plans. “Accuracy is much higher because you're basing it right off of design intent,” he said.

Burchfiel declined to release pricing information. The startup has a Web site at www.severity1.com .

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