DESIGN TOOLS: Sierra puts finishing touch on SoCs - Embedded.com

DESIGN TOOLS: Sierra puts finishing touch on SoCs

Santa Cruz, Calif. — It's one thing to design individual blocks for large systems-on-chip and another to tie them together into a working device. Sierra Design Automation Inc. tackles the latter challenge with its Pinnacle Chip Assembly solution, which it says combines the advantages of flat and hierarchical design.

An option for Sierra's Pinnacle physical-synthesis suite, Chip Assembly leverages Sierra's data model, which can model up to 50 million gates flat. It provides top-level optimization, full-chip clock tree synthesis and full-chip static timing analysis. What it doesn't include is top-level routing; for that, users will need a third-party router.

“What we are talking about is assembling the top level of a hierarchical design in terms of clocking,” said Sierra CTO Shankar Krishnamoorthy. “We address block-level timing budget mismatches, pin assignment mismatches, top-level timing violations and top-level DRC [design rule check] violations.”

Current hierarchical flows, according to Krishnamoorthy, are problematic for chip assembly tools. Challenges include the need for physical and timing abstractions, unachievable block-level budgets, pin assignment that's decoupled from timing optimization, manual editing of the top-level clock tree and an analysis deficit for multiple modes and process corners.

“With any kind of divide-and-conquer approach to chip design, you're introducing inaccuracy,” said Krishnamoorthy. “You're making guesses on the boundary constraints for the blocks and on how the pins should be assigned.”

Pinnacle Chip Assembly keeps the user's physical hierarchy intact but does not require the user to abstract anything, Krishnamoorthy said. It's up to the user to decide whether to work with a flat or hierarchical representation. “We can assemble the entire chip and view it as a flat problem, with all boundaries clearly demarcated,” he said.

Previously, he said, top-level optimization required two design representations for blocks: the original plus an abstracted model for the top level. Optimization was restricted for the top-level models. Pinnacle Chip Assembly doesn't need the abstracted models, Krishnamoorthy said. Changes made to blocks are directly updated in the block-level implementations. The product also concurrently analyzes and optimizes the top level for multiple modes and corners, addressing the timing violations that result from bad block budgets.

Top-level optimization in Pinnacle Chip Assembly also can optimize pin assignments. Normally, Krishnamoorthy noted, pins are assigned during floor planning, without knowledge of chip timing, opening the door to timing violations. The Pinnacle product can analyze critical paths and determine whether a different pin assignment will allow im- proved timing closure at the top level.

A key feature of Pinnacle Chip Assembly is full-chip clock tree synthesis. Because it's not necessary to abstract blocks, Krishnamoorthy said, users can keep block-level clock trees intact. They don't need to guess about delay or skew of a given clock tree. They can then build the top-level clock tree with the lower-level clock trees fully visible.

More significant is that the full-chip clock tree synthesis permits a top-down approach in which the user builds the best possible clock tree across the chip, without partitioning the clock tree into blocks. Existing tool flows don't support that capability, Krishnamoorthy said.

“You can treat the clock tree synthesis of the entire chip as a flat problem, starting with the PLLs [phase-locked loops] on the boundary of a chip to every register in the chip,” he said. “Pinnacle can build a balanced clock tree across the whole chip and then push that clock tree back into the blocks.”

Multimode, multiple-corner analysis helps clock tree synthesis, Krishnamoorthy said. “You can build a clock tree that fully understands the modes and corners and works across all combinations.”

Also new is a full-chip static timing analysis engine.

Chip Assembly is available now. Add- on prices begin at $250,000. The tool does not require Pinnacle physical synthesis, Krishnamoorthy said, but yields the best result with it.

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