DESIGN TOOLS: Tool suite rolls for asynchronous logic -

DESIGN TOOLS: Tool suite rolls for asynchronous logic

Santa Cruz, Calif. — Asynchronous logic can have power and performance benefits, but asynchronous design tools are generally unavailable. U.K. startup Silistix Ltd. plans to change that with ChainWorks, a tool set that implements “self-timed” interconnect to construct a network-on-chip.

Several weeks ago Silistix previewed Chain, a self-timed, packet-based network-on-chip (NoC) built on extensive academic research into asynchronous logic (see Dec. 28, page 1). Chain can link existing synchronous intellectual property (IP) blocks and supports such common protocols as AHB, AXI and OCP. It promises lower power consumption and easier timing closure than conventional synchronous buses.

Silistix is following a royalty-free EDA business model as opposed to an IP approach, and the result is ChainWorks. It includes ChainDesigner, which provides design entry and exploration; ChainCompiler, which synthesizes the asynchronous interconnect; and ChainLibrary, which provides the basic building blocks for the interconnect.

David Fritz, vice president of marketing for Silistix, said Chain will be a godsend to system architects who need to design fast and power-efficient interconnects yet still provide timing closure. “ChainWorks is a formalized way of designing interconnects that are going to perform in the ways they need to perform,” Fritz said. The tool suite, he noted, lets users define custom topologies, set link widths and choose the number of pipeline stages between two points.

The only chip produced so far with ChainWorks is a smart-card test IC built in 180-nanometer CMOS technology. Even with weak drivers, it operated at more than 500 MHz. With stronger drivers, Fritz said, getting into the gigahertz range should be easy.

Beta customers are noting a nominal power savings of anywhere from 10 to 20 percent compared with conventional bus structures, Fritz said, and much more than that at peak traffic rates. Timing closure for the interconnect usually happens the first time static timing analysis is run, he said.

Because Chain uses handshaking instead of clocked signals, there is some area overhead. Fritz declined to give numbers but said the “increase is in the noise when considered with the overall number of gates.”

The first step in constructing a Chain network is ChainDesigner. Using a schematic or SystemVerilog, users define the endpoints of initiators and targets and their ports. Users also graphically define a topology. This could be a conventional tree topology, a crossbar or a custom topology.

Through component property sheets, users assign the widths of the links to tune power and performance. Users also define the location of pipeline stages.

The output of ChainDesigner is an internal representation that feeds into ChainCompiler, along with a SystemC model that can be used for functional verification. After synthesis, however, users can take the output of static timing analysis and feed it back into ChainDesigner to attach timing information to the interconnect. What's not yet available is a what-if analysis based on area or power.

ChainCompiler, said Fritz, is “the only self-timed synthesis tool for interconnect on the planet today.” Its only input is the representation that comes from ChainDesigner. There is no direct implementation of constraints in the first release. Timing constraints will be supported in a later release.

ChainCompiler draws on ChainLibrary, which provides the necessary information to map the abstract Chain network components defined in ChainDesigner to a generic implementation suitable for synthesis. Represented components include routes, merges, gateways, protocol adapters, switches and synchronizer/desynchronizers that allow signals to cross between domains.

ChainCompiler produces a gate-level netlist, which needs to be fed into a tool such as Synopsys' Design Compiler to be mapped into standard cells. It also produces data for static timing analysis and “hints” for downstream placement and routing tools.

“Since we are self-timed,” Fritz said, “we have to have some assumptions about wire delays, such as, 'This gate and that gate should be very close together.' ” But that doesn't mean placement and routing are more complicated. In fact the opposite may be true, he said, because a 32-wire line in a conventional bus structure could possibly be dropped to a single line where high bandwidth is not required.

ChainCompiler also generates manufacturing test patterns. It provides full scan capability for Chain networks, as well as scripts for third-party automatic test pattern generation tools to achieve more than 99 percent stuck-at fault coverage of Chain networks.

Fritz said ChainWorks doesn't require expertise in asynchronous logic, because the details are hidden by the tools. He said graduate students in Japan had easily grasped the basic concepts in a two-day training class.

ChainWorks will be available in the second quarter. Pricing has not been determined but will be “roughly similar to what you'd pay for Design Compiler,” Fritz said. Silistix has yet to name any customers. n

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